A0A11 Search Results

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

Contextual Info: SMJ416160, SMJ418160 1048576-WORD BY 16-BIT HIGH-SPEED DRAM 1 SGMS720A - APRIL 1995 - REVISED JUNE 1995 XXX PACKAGE TOP VIEW ACCESS ACCESS ACCESS TIME TIME TIME '41x160-60 41x160-70 '41x160-80 • • • • • • • • tRAC MAX 60 ns 70 ns SO n* *CAC

Contextual Info: TO SHIBA THMY644071EG-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY644071EG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416FT DRAMs and an unbuffer on a printed circuit board.

TC5116400

Abstract: tc5116400csj 300D1 toshiba RAS-25
Contextual Info: INTEGRATED TOSHIBA TO SH IBA M O S DIGITAL NTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 5 1 16 4 0 0 C S J / C S T - 4 0 T C 5 1 1 6 4 0 0 C S J / C S T - 50 T C 5 1 1 6 4 0 0 CSJ / C S T * 60 DATA SILICON GATE C M O S TENTATIVE D ATA 4,194,304 W O R D x 4 BIT D Y N A M IC R A M

TLCS-47

Contextual Info: TOSHIBA TMP47P452VN, TMP47P452W For program operation, the programming is achieved by using with EPROM programm er TMM2764AD type and adapter socket (BM1120, BM1121). CMOS 4-Bit Microcontroller TMP47P452VN, TMP47P452VF The 47P452V is the OTP microcontroller with 32kbits PROM.

r2a3

Abstract: r1a10 M1367 M4589
Contextual Info: TOSHIBA THMY728010BEG-80L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,608-WORD BY 72-BIT SYNCHRONOUS D RA M MODULE DESCRIPTION The THMY728010BEG is a 8,388,608-word by 72-bit synchronous dynamic RAM module consisting of nine TC59S6408BFTL DRAMs and PLL/Registers on a printed circuit board.

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

Contextual Info: TOSHIBA TC51V16400BST-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description TheTC 51V16400B ST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. T heTC 51V16400B ST uti­ lizes Toshiba's CM O S silicon gate process technology as well as advanced circuit techniques to provide wide operating mar­

2269H

Contextual Info: TOSHIBA THMY7216C1EG-80H TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216C1EG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408FT DRAMs and an unbuffer on a printed circuit board.

2332 eprom

Abstract: PIN-20 IC DIAGRAM 2332 rom 2732A eprom
Contextual Info: TMS2332 4096-WORD BY 8-BIT READ-ONLY MEMORY SEPTEMBER 1984 - REVISED NOVEMBER 1985 4 0 9 6 X 8 Organization N PACKAGE All Inputs and Outputs TTL Compatible TOP VIEW A 7 C 1 ^ 2 4 3 v Cc A6£ 2 23 3 A 8 A5 £ 3 22 > 9 Fully Static (No Clocks. No Refresh)

TCK-1000

Abstract: D038 toshiba M7
Contextual Info: TO SH IBA THM Y6480F1 BEG-80 TEN TA TIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388, 6 O8-W O RD B Y 64-BIT SYN CH R O N O U S DRAM M ODULE D ESCRIPTIO N The THMY6480F1BEG is a 8,388,608-word by 64-bit synchronous dynamic RAM module consisting of eight TC59S6408BFT DRAMs and an unbuffer on a printed circuit board.

SM81600E

Abstract: IS42SM16800E IS42SM81600E IS42SM16800E-7TLI IS42SM32400E IS42SM32400E-7T IS42SM16800E-7BLI
Contextual Info: IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E 16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM APRIL 2011 DESCRIPTION FEATURES • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge

IS42VS16100E

Abstract: 42VS16100E IS42VS16100E-75BLI
Contextual Info: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11

Contextual Info: TMS416160, TMS416160P 1 048 576-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES SMKS660-DECEMBER 1992 Organization. . . 1 048 576 x 16 RE P A C K A G E t DC P A C K AG E t TOP VIEW (TOP VIEW) Single 5-V Supply (10% Tolerance) '416160/P-60 '416160/P-70

AS4SD32M16

Contextual Info: SDRAM AS4SD32M16 512Mb: 32 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 32 Meg x 16 (8 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive

Contextual Info: SDRAM AS4SD8M16 128 Mb: 8 Meg x 16 SDRAM PIN ASSIGNMENT Top View Synchronous DRAM Memory 54-Pin TSOP FEATURES • • • • • • • • • • • • • • Full Military temp (-55°C to 125°C) processing available Copper lead frame option for enhanced reliability

IS42S32400D

Abstract: 42S32400D is42s32400d-6bli IS42S32400D-7TLI
Contextual Info: IS42S32400D 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge MARCH 2009 OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed

DDR200

Abstract: DDR266A DDR266B IBMN612404GT3B IBMN612804GT3B IBMN62540 IBMN62580 128MB PC266
Contextual Info: IBMN612404GT3B IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM Preliminary Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency MHz * DDR266A (7N) DDR266B (75N) DDR200 (8N) 133 143 100 133 100 125 * Values are nominal (exact tCK should be used).

Contextual Info: . IBM13M64734CCA 64M x 72 2-Bank Registered/Buffered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 64Mx72 Synchronous DRAM DIMM • Performance: -260 Device Latency fCK Clock Frequency tAC Clock Access Time 2 -360 -360 Units

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

ba1s

Contextual Info: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data

Nanya nt5ds8m16fs

Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
Contextual Info: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8M16 NT5DS8M16FS
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

NT5SV8M16FS

Abstract: Nanya NT5SV8M16FS NT5SV8M16FS-75BI Nanya NT5SV8M16FS-75Bi NT5SV8M16FS-6KI NT5SV8M16FT NT5SV8M16FT-6KI nt5sv8m16fs-6k 54-PIN NT5SV8M16FT-6K
Contextual Info: NT5SV8M16FT-6KI NT5SV8M16FS-6KI NT5SV8M16FT-75BI NT5SV8M16FS-75BI 128Mb Synchronous DRAM • • • • • • • • • • • • Features • High Performance: Maximum Operating Speed CAS Latency PC166 6KI PC133 (75BI) 2 7.5 10 ns 3 6 7.5 ns •