74S28 Search Results

Contextual Info: 74S280 Signetics Parity Generator/Checker 9-Bit Odd/Even Parity Generator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180 for easy system up-grading

1N3064

Abstract: 1N916 74LS 74S280 N74S280N S280 parity generator
Contextual Info: 74S280 Signetìcs Parity G enerator/C hecker 9-Bit Odd/Even Parity G enerator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180

74S280

Abstract: 74LS N74S280N S280 4 bit even and odd parity checker
Contextual Info: 74S280 Signetics Parity Generator/Checker 9-Bit O dd/Even Parity Generator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180

74s281

Abstract: DM74 DM74S182 DM74S194 S281 LI 20 AB S28I 280J2
Contextual Info: ^ M SI DM 74S281 4 -B it Parallel Binary A ccum ulators General Description These S c h o ttk y c la m p e d fou r-b it accum ulators integrate high-perform ance versions o f an arith m e tic logic unit/ fu n ctio n generator, and a shift/storage m atrix in a single

74S288

Abstract: 74S288 PROGRAMMING DM74S288N 288AN DM54S288J SAFEA DM74S288J DM74S288V DM74S288 N16A
Contextual Info: DM54S288/74S288 1/WX National Z ta Semiconductor DM54/74S288 32 x 8 256-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 32 words by 8 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the

Contextual Info: 280 CONNECTION DIAGRAM PINOUT A 54S/74S280 b \ l ^ ° 9-BIT PARITY GENERATOR/CHECKER DESCRIPTION — The ’280 is a high speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number or these inputs are HIGH. If an even number of inputs are HIGH, the Sum

Contextual Info: 74S280 Signetics Parity Generator/Checker 9-Bit Odd/Even Parity Generator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180 for easy system up-grading

Contextual Info: SN54LS280, SN 54S280, SN 74LS280. SN 74S280 9-BIT ODDfEVEN PARITY GENERATORS/CHECKERS DECEMBER 1972 - REVISED MARCH 1988 • Generates Either Odd or Even Parity fo r Nine Data Lines SN 54LS 280, SN 54S 280 . . . J OR W PACKAGE SN 74LS280. S N 74S 280 . . . D OR N PACKAGE

54S280DM

Abstract: 54S280FM 74S280DC 74S280FC 74S280PC
Contextual Info: 280 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S280 b l ! ^ ° 1~4~| V c c le [ 7 9-BIT PARITY GENERATOR/CHECKER HI'S l?U n c |T jjO U Ib [ T 13 £e [T ] jÖ '2 T ]|1 2 o [I T]io GND [ 7 D E S C R IP T IO N — T he ’280 is a h ig h speed p a rity g e n e ra to r/c h e c k e r th a t

Contextual Info: 74S280 Signetìcs Parity Generator/Checker 9-Bit O dd/Even Parity G enerator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180

Contextual Info: 289 CONNECTION DIAGRAM PINOUT A 54S/74S289 b i 1 5 4 L S /7 4 L S 2 8 9 C u <7 ao[T T i l vcc 64-BIT RANDOM ACCESS MEMORY «D E Tsl Ai With O pen-Collector Outputs WE [ T 14] A 2 Di [7 13] A 3 0 ,[T T2ID 4 D2 [ ? T T lo a Ö2 U Tö] D 3 D ESC R IPTIO N — The '289 is a high speed 64-bit RAM organized as a 16word by 4-b it array. Address inputs are buffered to minim ize loading, and

Contextual Info: GD54/74S280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS Feature Pin Configuration • Generates Either Odd or Even Parity for Nine Data • • Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems Us­ ing MSI Parity Circuits a Description These universal, monolithic, nine-bit parity

74LS289

Abstract: 74S289PC 54LS289DM 54S289DM 74LS289DC 74LS289FC 74LS289PC 74S289DC 74S289FC S289T
Contextual Info: 289 b 11 54S/74S289 54LS /74LS 289 <T' C O N N E C T IO N D IA G R A M P IN O U T A U <7 ao[T 64-BIT RANDOM ACCESS MEMORY Til vcc Tsl Ai csGE 771 A2 771 a 3 T2ID4 [7 [7 5, [I 02 [][ 52|T W ith O p e n -C o lle c to r O utputs we Oi D E S C R IP T IO N — T he ’289 is a h igh speed 6 4 -b it RAM o rg a n ize d as a 16w o rd by 4 -b it array. A d d re ss in p u ts are b u ffe re d to m in im ize lo a d in g , and

DM74S287AN

Abstract: DM74S287 led matrix 32X32 H11Q1 DM74S287J DM74S287V J16A N16A DM74S287A 287AN
Contextual Info: 74S287 20 National Æ Æ Semiconductor D M 74S287 256 x 4 1024-Bit T T L PROM General Description Features This S ch o ttky m em ory is organized in the popular 256 w ords by 4 bits configuration. M em ory enable inputs are provided to co ntro l the output states. W hen the device is

74S287

Abstract: 74S287 programming instructions 74S287 programming DM74s287 DM74S287AN DM74S287N DM54S287J J16A N16A 74s* programming
Contextual Info: DM54S287/74S287 National ÆjA Semiconductor DM54/74S287 256 x 4 1024-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 256 words by 4 bits configuration. Memory enable inputs are provided to control the output states. When the device is

Contextual Info: NATIONAL SEMICOND {LOGIC} GSË D J b S D U S E □DbBTfiG □ | 280 T -V s -'/7 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S280 9-BIT PARITY GENERATOR/CHECKER 1 t« T vQvcc l7[T U lis n c [T 12]U is[T n ib se| J H l2 lo ti a - OND^ D E S C R IP T IO N — The '280 is a high speed parity generator/checker that

74s281

Abstract: SN74S281
Contextual Info: TYPES SN54S281, 74S281 4-BIT PARALLEL BINARY ACCUMULATORS F E B U A R Y 1 9 7 4 - R E V IS E D D EC EM B ER 1 983 SN 54S281 I OR W PA CKAG E SN 74S281 . . . DW , J OR N PA CKA G E Full 4-Bit Binary Accumulator in a Single Package T O P V IEW 15 Arithmetic/Logic-Type Operations:

SN74S289B

Abstract: S289B sn74s189 SN74S189B
Contextual Info: SN 54S 189B , S N 54S 289B , S N 74S 189B , SN 74S289B 64-BIT HIGH PERFORMANCE RANDOM ACCESS MEMORIES SEPTEMBER 1 9 7 6 - REVISED FEBRUARY 19 8 4 S T A T IC R A N D O M -A C C E S S M E M O R IE S

74283 IC pin diagram

Abstract: IC 74283 74283 IC 8 bit pin diagram
Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN 74LS283, 74S283 4 BIT BINARY FU LL AD DERS W ITH FA S T CARRY OCTOBEH 1976 - REVISED MARCH 1988 S N 5 4 2 8 3 , S N 5 4 L S 2 8 3 . . . J OR W PAC KA G E S N 5 4 S 2 8 3 . . . J P AC K A G E S N 7 4 2 8 3 . . . N P AC K A G E

74S206

Abstract: 74s201
Contextual Info: 54/74S ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) PARAMETER TEST CONDITIONS LOW LEVEL VÇC~MIN MIN TYP MAX OUTPUT VOLTAGE V|C(V) V|H (V) HIGH LEVEL CLAMP VOLTAGE V çç= M IN VCC = “ IN l|=-18 mA MIN TYP MAX MIN TYP VOH (V) HIGH LEVEL

Contextual Info: GEC PLESSEY w . S E M I C O N D U C T O R S DS 3303 -1 NJ8820GG FREQUENCY SYNTHESISER PROM INTERFACE The NJ8820GG is a synthesiser circuit fabricated w ith the 2-micron CMOS process and is capable of achieving high sideband attenuation and low noise performance. The circuit

sn76131

Abstract: tlo72cp TOSHIBA 2N3055 M53207P 2N3055 TOSHIBA KIA7313AP kia7640ap LA5530 M5L8155P TBB1458B
Contextual Info: ACTIVE ELECTRONICS COMPONENTS CROSS REFERENCE GUIDE 2SC429GTM 2SC458 2SC458LG 2SC503 2SC504 2SC510 2SC512 2SC519 2SC520A 2SC594 2SC699A 2SC780 2SC809-1 2SC945 2SC3012 2SC3074 2SC3114 2SC3115 2SC3116 2SC3117 2SC3134 2SC3135 2SC3138 2SC3143 2SC3144 2SC3145 2SC3157

MH1SS1

Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
Contextual Info: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik

74S301

Abstract: TBP28S42 SIGNETICS prom 1024x8 PROM n82s123 82LS181 N82LS181 S82LS181 N82S141 TBP28P86
Contextual Info: MAY 1982 BIPOLAR MEMORY DIVISION 8 1 9 2 -BIT BIPOLAR P R O M 1 0 2 4 X 8 DESCRIPTION The 82LS181 is field programmable, which mea ns that custom patterns are immediately available by following the fusing procedure given in this data manual. The 82LS18I is