54S280FM Search Results

Contextual Info: 280 CONNECTION DIAGRAM PINOUT A 54S/74S280 b \ l ^ ° 9-BIT PARITY GENERATOR/CHECKER DESCRIPTION — The ’280 is a high speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number or these inputs are HIGH. If an even number of inputs are HIGH, the Sum

54S280DM

Abstract: 54S280FM 74S280DC 74S280FC 74S280PC
Contextual Info: 280 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S280 b l ! ^ ° 1~4~| V c c le [ 7 9-BIT PARITY GENERATOR/CHECKER HI'S l?U n c |T jjO U Ib [ T 13 £e [T ] jÖ '2 T ]|1 2 o [I T]io GND [ 7 D E S C R IP T IO N — T he ’280 is a h ig h speed p a rity g e n e ra to r/c h e c k e r th a t

Contextual Info: NATIONAL SEMICOND {LOGIC} GSË D J b S D U S E □DbBTfiG □ | 280 T -V s -'/7 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S280 9-BIT PARITY GENERATOR/CHECKER 1 t« T vQvcc l7[T U lis n c [T 12]U is[T n ib se| J H l2 lo ti a - OND^ D E S C R IP T IO N — The '280 is a high speed parity generator/checker that