288MB Search Results

MICRON BGA PART MARKING

Contextual Info: 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2 Features CIO RLDRAM 2 MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks Features Options1 • 533 MHz DDR operation 1.067 Gb/s/pin data rate

K4R571669A-FCK8

Abstract: K4R881869A-FCK8 K4R881869A-FCM8 K4R881869A-FCM9 K4R881869A-FCN9 K4R881869A-FCT9
Contextual Info: Direct RDRAM K4R571669A/K4R881869A 256/288Mbit RDRAM A-die 512K x 16/18bit x 32s banks Direct RDRAMTM Version 1.4 July 2002 Page -1 Version 1.4 July 2002 Direct RDRAM™ K4R571669A/K4R881869A Change History Version 1.11( September 2001) - Preliminary

code A106

Abstract: MD18R3268AG0-CM8 MD18R3268AG0-CN1 MD18R3268AG0-CT9 MD18R326GAG0-CM8 MD18R326GAG0-CN1 MD18R326GAG0-CT9 serial presence detect samsung 2010 MARKING A106
Contextual Info: Preliminary MD18R3268 G AG0 Change History Version 0.1 (Sept. 2003)- Preliminary * First copy. * Based on version 1.0 (July 2002) 256/288Mbit D-die 32 Bit RIMM Module Datasheet Version 0.1 Sept. 2003 MD18R3268(G)AG0 Preliminary (32Mx18)*8(16)pcs 32 Bit RIMM Module based on 576Mb A-die, 32s banks,32K/32ms Ref, 2.5V

Contextual Info: MS18R1622 4/8 DH0 Revision History Version 1.0 (July 2002) - Based on the 1.1 ver. (July 2002) 288Mbit A-die SO-RIMM Module Datasheet. Page 0 Rev. 1.0 July 2002 MS18R1622(4/8)DH0 (16Mx18)*2(4/8)pcs SO-RIMM™ based on 288Mb D-die, 32s banks,16K/32ms Refresh, 2.5V

TC59LM836DKB

Abstract: TC59LM836DKB-33
Contextual Info: TC59LM836DKB-33,-40 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2 − 2,097,152-WORDS x 4 BANKS × 36-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network

Contextual Info: Preliminary GS82582DT19/37E-450/400/375/333 288Mb SigmaQuad-II+TM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

BW211

Abstract: GS82582Q38E-500I
Contextual Info: Preliminary GS82582Q20/38E-500/450/400/375 288Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: Preliminary GS82582T19/37E-450/400/375/333 288Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

EL B17

Contextual Info: UGD128R16 8 08U6J(7J) Data sheets can be downloaded at www.unigen.com 256/288MB Bytes (128M x 16/18 bits) RAMBUS SO-RIMM MODULE 160 Pin SO-RIMM based on 8 pcs 8M x 16/18 RDRAM & 16K Refresh 128M x 16 bits, 128M x 18bits w/ECC, 800MHz and 600MHz GENERAL DESCRIPTION

200-ball

Abstract: A79 marking code MN18R1628EF0 samsung resitor
Contextual Info: MN18R1624 8 EF0 MP18R1624(8)EF0 Revision History Version 0.1 (February 2004) -Preliminary - First Copy - Based on the 1.2 ver. (Dec. 2003) 288Mbit D-die NexMod Module Datasheet. Version 1.0 (May 2004) - Eliminate "Preliminary" Page 0 Version 1.0 May 2004

09005aef809f284b

Contextual Info: 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9‡ Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

MT49H16M18C

Contextual Info: 16 Meg x 18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features 288Mb SIO Reduced Latency RLDRAM II MT49H16M18C For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)

a65 1021

Contextual Info: MR16R1622 4/8/G AF0(1) MR18R1622(4/8/G)AF0(1) Preliminary Change History Version 1.1 (August 2001) * First copy. * Based on the 1.0ver Rambus 256/288Mbit RDRAMs base RIMM Datasheet Version 1.2 (February 2002) * Add 1066-35 binning Version 1.3 (April 2002)

MICRON BGA PART MARKING

Abstract: NF 034 T6N 700 MT49H16M18
Contextual Info: 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II Features CIO RLDRAM II MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks Features Options1 • 533 MHz DDR operation 1.067 Gb/s/pin data rate

smd dk qk

Abstract: SMD MARKING CODE ACY smd marking codes BA5 smd marking codes BA2 RLDRAM MT49H16M18C
Contextual Info: ADVANCE‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization - 16 Meg x 18, 32 Meg x 9 Separate I/O

MT49H16M18C

Contextual Info: PRELIMINARY‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization • 16 Meg x 18, 32 Meg x 9 Separate I/O

Contextual Info: K4C89093AF Target 288Mb Network-DRAM-II Specification Version 0.2 - 1 - REV. 0.2 Aug. 2003 K4C89093AF Target Revision History Version 0.0 Nov. 2002 - First Release Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc.

Contextual Info: K4C89183AF 288Mb Network-DRAM-II Specification Version 0.11 - 1 - REV. 0.11 Apr. 2003 K4C89183AF Revision History Version 0.0 Oct. 2002 - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.

direct rdram rac

Contextual Info: MD16R1624 8/G AF0 MD18R1624(8/G)AF0 Change History Version 1.0 (April 2002) * First copy. * Based on 1.0 version Rambus 256/288Mbit 32 Bit RIMM Module Datasheet Version 1.1 (July 2002) * Based on the 1.0 ver.(April 2002) 256/288Mbit A-die 32 Bit RIMM Module Datasheet

DRAM material declaration

Contextual Info: MR16R1624 8/G EG0 MR18R1624(8/G)EG0 Change History Version 0.1 (December 2003) - Preliminary * First copy. * Based on the 1.0 ver. (July 2002) 256/288Mbit D-die RIMM Module Datasheet Version 1.0 (May 2004) * Eliminate "Preliminary" Page 0 Version 1.0 May 2004

MARKING CODE 11gb

Contextual Info: MR18R326GAG0 Preliminary Change History Version 0.1 September 2003 - Preliminary * First copy. * Based on the 1.0 ver. (July 2002) 256/288Mbit D-die RIMM Datasheet Page 0 Version 0.1 Sept. 2003 MR18R326GAG0 Preliminary (32Mx18)*16pcs RIMMTM Module based on 576Mb A-die, 32s banks,32K/32ms Ref, 2.5V

LLDRAM

Contextual Info: Preliminary GS4288C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II

TOP SIDE MARKING OF MICRON

Abstract: 84 FBGA 84-PIN MT6V16M16F2-3C MT6V16M16F2-3M MT6V16M18F2-3M RDRAM FBGA 84 MICRON fBGA package code
Contextual Info: ADVANCE 256Mb/288Mb: 16 MEG x 16/18 RDRAM RAMBUS DRAM MT6V16M16 - 512K x 16 x 32 banks MT6V16M18 - 512K x 18 x 32 banks For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html FEATURES 84-PIN FBGA TOP VIEW

Contextual Info: Preliminary GS4288C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II