MARKING A3A Search Results

A09 N03 MOSFET

Abstract: marking B3A sot23-5 t7G SOT23-6 marking H2A sot-23 ADM2004 marking moy sot-23 A06 N03 MOSFET SOT23-5 D2Q M05 SOT-23 M2A MARKING SOT-23
Contextual Info: Tiny Part Number Cross Reference Package Marking Model Function Package Description Package Marking Model Function Package Description 0Axx 0Bxx 2A0A 2B0A 2C0A 3A0A 3B0A 3C0A 4A0A 4B0A 4C0A 5A0A 5B0A 5C0A 9Jxx 9Lxx 9Mxx 9Rxx 9Sxx 9Txx 9Zxx A00 A01 A02 A04

NT6SM32M16AG-S1

Abstract: NT6SM16M32 128M32 NT6SM16M32AK NT6SM32M16AG Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb
Contextual Info: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of  Marking VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed

Lpddr2 Idd7

Abstract: COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32
Contextual Info: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed

Lpddr2 Idd7

Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

Lpddr2 Idd7

Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2
Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

NTC 200-9

Abstract: a2240 128M16 A1930 NT6SM16M32
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

lpddr2 256mb

Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2
Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ

A1930

Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

NT6DM16M16AD-T1

Abstract: 64M32 HP 3458 NT6DM16M16AD-T1I
Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ

P6SBMJ24A

Abstract: B17C B14A A17a B14A equivalent MARKING A19c marking A32A P4SSMJ24A A12A a32a
Contextual Info: SURFACE MOUNT DEVICES FOR HYBRID APPLICATIONS PLASTIC MATERIAL USED CARRIES UL 94V-0 TYPE Marking Break Down Voltage VBR V @ IZT Test Current Min Nom Max Volts Volts Volts @IT Working Peak Reverse Voltage Maximum Reverse Leakage Current Maximum Reverse Current

NT6SM16M16AG-S1

Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64
Contextual Info: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle

B14A equivalent

Abstract: zener b14a P6SBMJ24A B17C tvs2315pt TVSS5VESPT diode B14A B14A zener equivalent A17a P4SSMJ24A
Contextual Info: SURFACE MOUNT DEVICES FOR HYBRID APPLICATIONS PLASTIC MATERIAL USED CARRIES UL 94V-0 Zener Voltage VZ V @ IZT TYPE Test current Working Peak Reverse Voltage IZT(mA) Vrwm(V) Marking Min Nom Max Volts Volts Volts Maximum Maximum Maximum Reverse reverse Reverse

NT6DM16M

Contextual Info: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver

NT6DM32M16AD-T1

Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout
Contextual Info: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver

Contextual Info: FLASH PRELIMINARY AS8FLC1M32A Hermetic, Multi-Chip Module MCM FIGURE 1: PIN ASSIGNMENT (Top View) •      OPTION Access Speed 70ns 90ns 100ns 120ns MARKING -70 -90 -100 -120 61 62 63 64 65 66 67 68 01 02 03 04 05 06 07 59

Contextual Info: 16 M E G :x4,x8 MICRON I TECHNOLOGY, INC. Q FEATURES 44-Pin TSOP x4 NC DQ0 NC DQ1 - MARKING 4M 4 2M 8 - - • W RITE Recovery OWR/tDPL *WR = 1 CLK *WR = 2 CLK C on tact facto ry for availability.) Al A2 • Plastic Package - OCPL 44-pin TSOP (400 mil) Note:

krc 118 048

Abstract: ZM02
Contextual Info: ADVANCE 2. 4 WIEG X 64 SDRAM DIMMs l^ iid R o r s i SYNCHRONOUS DRAM MODULE MT8LSD T 264A MT16LSD(T)464A FEATURES OPTIONS (DE-9) 2 Meg x 64 TSO P (shown), (DE-10) 4 Meg x 64 TSOP, (DE-25) 2 Meg x 64 SOJ, (DE-26) 4 Meg x 64 SOJ Sm Tm Q pj MARKING • Components

Contextual Info: - PRELIMINARYD ecem ber 1995 Edition 2.1 FUJITSU _ P R O D U C T P R O F IL E S H E E T : MB81G83222-010/-012/-015 CMOS 2 X 128K X 3 2 SYNCHRONOUS GRAM CMOS 2 BANKS OF 131,072-WORDS x 32-BIT SYNCHRONOUS GRAPHIC RANDOM ACCESS MEMORY Marking side The Fujitsu MB81G83222 is a CMOS Synchronous Graphic Random Access Memory

Contextual Info: PRELIMINARY MICRON I TECHNOLOGY, 1 6 M l n b XAM INC. FEATURES 50-Pin TSOP V cc DQ0 DQ1 V ssQ DQ2 DQ3 V ccQ DQ4 DQ5 V ssQ DQ6 DQ7 V ccQ DQ M L W E# C AS# RAS# C S# BA A10 A0 A1 A2 A3 V cc MARKING 1M16 • Plastic Package - OCPL 50-pin TSOP 400 mil TG • Timing

48LC

Abstract: MT18LSDT472
Contextual Info: ADVANCE 2. 4 M E G X 72 S D R A M DIM Ms |U |IC = R O N SYNCHRONOUS DRAM MODULE MT9LSD T 272A MT18LSD(T)472A FEATURES OPTIONS (DE-7) 2 Meg x 72 TSOP (shown), (DE-8) 4 Meg x 72 TSOP, (DE-27) 2 Meg x 72 SOJ, (DE-28) 4 Meg x 72 SOJ MARKING • Components SO J

Contextual Info: ADVANCE 2 MEG X 64 S D R A M SO DIM M IC Z R O fM SMALL-OUTLINE SDRAM MODULE MT8LSDT264H FEATURES OPTIONS 144-Pin Small-Outline DIMM DF-6 umilimi MARKING • Package 144-pin SODIM M (gold) G • F requen cy/C A S Latency 66 M H z /C L = 2 (10ns, 100 M Hz SDRAM s) -66CL2

Contextual Info: ADVANCE M IC R O N I MT41 LC256K32D4 S 256K x 32 SGRAM f ^ D A D U I f ^ C n A R /l w r iM IV I n M r n l V / O 256K x 32 SGRAM PULSED RAS, DUAL BANK, p i p e lin e d ,3 .3 V o p e r a t io n NEW SYNCHRONOUS FEATURES OPTIONS MARKING • Timing 10ns access

Contextual Info: Filter connectors Solder cup with threaded insert accepts cable AWG 26 Socket connector Plug connector Kat 1 i A4A Kat 1 i A3A B + 0,25 A - 0,76 B - 0,25 C 9 31,19 16,46 25,00 9 31,19 16,79 25,00 6,12 15 39,52 24,79 33,30 15 39,52 25,12 33,30 \%\% 6,12 25

Omron

Abstract: 91a100 touch switch pushbutton 32AAA 90K-1 A3AA-91A1-00E
Contextual Info: A3A Lighted Pushbutton Switch Compact High-capacity Push-button Switch ●Ideal for use as a high breaking capacity Power Switch. ●Switches from micro load minimum applicable load: 5 VDC 1mA to high capacity load. RoHS Compliant A 3 A Refer to Safety Precautions for All Pushbutton Switches and