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    Mercury Systems Inc W764M32V-100SBI C50700

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    Avnet Americas W764M32V-100SBI C50700 Tray 500 52 Weeks, 1 Days 1
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    Alliance Memory Inc AS4C64M32MD1A-5BIN

    DRAM Chip LPDDR SDRAM 2Gbit 64M x 32 1.8V 90-Pin FPBGA Tray - Trays (Alt: AS4C64M32MD1A-5BIN)
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    Micron Technology Inc MT46H64M32LFBQ-48 AIT:C

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    Win Source Electronics MT46H64M32LFBQ-48 AIT:C 1,000
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    Vishay Intertechnologies CRCW12064M32FKEB

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    Alliance Memory Inc AS4C64M32MD1-5BCN

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    Mouser Electronics AS4C64M32MD1-5BCN
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    64M32 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    A1833

    Contextual Info: Advance‡ 2Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 banks MT46H256M16L2 – 32 Meg x 16 x 4 banks x 2 64M32LF – 16 Meg x 32 x 4 banks MT46H128M32L2 – 16 Meg x 32 x 4 banks x 2 MT46H256M32L4 – 16 Meg x 32 x 4 banks x 4


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    mt46h128m16lfmt46h256m16l2mt46h64m32lfmt46h128m32l2+3mt46h256m32l409005aef83a73286a1833 PDF

    Contextual Info: 64M32V-XSBX Not Recommended for New Designs — Replaced by 64M32V1-XBX 64Mx32 NOR Flash Multi-Chip Package 3.0V Page Mode Flash Memory  Hardware features FEATURES  Single power supply operation • Advanced Sector Protection • WP#/ACC input accelerates programming time when


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    w764m32v-xsbxw764m32v1-xbx64mx32 PDF

    W764M32V1-XBX

    Contextual Info: 64M32V1-XBX *PRELIMINARY 64Mx32 NOR Flash Multi-Chip Package 3V Page Mode Memory FEATURES GENERAL DESCRIPTION  Single power supply operation The 64M32V1-XBX device is a 3V single power flash memory. The device utilizes two chips organized as 67,108,864 words. The


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    w764m32v1-xbx64mx3232-bit16-bit+21024-byteprx32 PDF

    Contextual Info: 64M32L2SB-XX *PRELIMINARY 2Gb LPDDR 2 x 32Mx32 FEATURES  Package: GENERAL DESCRIPTION • 152 Plastic Ball Grid Array (PBGA), 14 x 14 mm Microsemi 64M32L2SB package-on-package (PoP) MCP product combines two Mobile LPDRAM devices in a single MCP.


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    ms46h64m32l2sb-xx32mx32ms46h64m32l2sb268m-bit PDF

    D9KG

    Abstract: marking code micron label marking aa5 152-Ball M2P20 MT46H64M32L2CG-6 152-Ball PoP SMD marking code B10 AA5 mark diagram smd marking code M21
    Contextual Info: Preliminary‡ 152-Ball x32 LPDDR-SDRAM PoP TI-OMAP Features LPDDR-SDRAM 152-Ball Package-on-a-Package (PoP) TI-OMAP MT46HxxxMxxLxCG Features Options • Vdd/Vddq = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR)


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    152-ballmt46hxxxmxxlxcg09005aef833913f1/source09005aef833913d6+9d9kgmarking code micron labelmarking aa5m2p20mt46h64m32l2cg-6152-ball popsmd marking code b10aa5 mark diagramsmd marking code m21 PDF

    MT46H128M16

    Abstract: MT46H128M16LF MT46H64M32LF MT46H128 MT46H128M32L2 MT46H256M32 MT46H64M32 MT46H128M MT46H128M16L 240-ball
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks 64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 - 32 Meg x 16 x 4 Banks x 4


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    mt46h128m16lfmt46h64m32lfmt46h128m32l2mt46h256m32l4+9mt46h256m32r409005aef8457b3ebmt46h128m16mt46h128mt46h256m32mt46h64m32mt46h128mmt46h128m16l240-ball PDF

    216-ball

    Abstract: Dual LPDDR2 LPDDR2 SDRAM micron LPDDR2 1Gb Memory MT42L128M64D4 MR63 Micron LPDDR2 lpddr2 168 lp-ddr2 MT42L256M32
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, 64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


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    mt42l128m16d1mt42l64m32d1mt42l64m64d2mt42l128m32d2+14mt42l256m32d4mt42l128m64d4mt42l96m64d3mt42l192m32d309005aef83f3f2eb216-balldual lpddr2lpddr2 sdram micronlpddr2 1gb memorymr63micron lpddr2lpddr2 168lp-ddr2mt42l256m32 PDF

    Lpddr2 Idd7

    Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1
    Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle


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    512mbnt6sm16m32ak-16meg-90-ball+6x13mm16m32lpddr2 idd7216-ball lpddr2nt6sm16m32nt6sm16m32ak-s1 PDF

    Contextual Info: White Electronic Designs 64M32V-XSBX 64Mx32 Flash Multi-Chip Package 3.0V Page Mode Flash Memory FEATURES Single power supply operation Software features • 3 volt read, erase, and program operations • Program Suspend and Resume: read other sectors before programming operation is


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    64mx32128-word/256-byte8-word/16-byte64-bit PDF

    mt42l128M32

    Abstract: mt42l256m32 MT42L64M32D1 LPDDR2-1066 MT42L256M32D4 MT42L128M32D MT42L128M16D1 MT42L128M64D4 MT42L256M32D MT42L128M32D2
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, 64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


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    mt42l128m16d1mt42l64m32d1mt42l64m64d2mt42l128m32d2+10mt42l256m32d4mt42l128m64d4mt42l96m64d3mt42l192m32d309005aef83f3f2ebmt42l128m32mt42l256m32lpddr2-1066mt42l128m32dmt42l256m32d PDF

    MT42L64M64D2

    Abstract: mt42l128M32 LPDDR2-1066 64M32 MT42L128M64D4 MT42L MT42L256M32D4 MT42L64M32D1 LPDDR2 SDRAM micron micron lpddr2
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, 64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


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    mt42l128m16d1mt42l64m32d1mt42l64m64d2mt42l128m32d2+11mt42l256m32d4mt42l128m64d4mt42l96m64d3mt42l192m32d309005aef83f3f2ebmt42l128m32lpddr2-106664m32mt42llpddr2 sdram micronmicron lpddr2 PDF

    CSN-11

    Abstract: MT46H64M32L2KQ 168B micron lpddr lpddr smd code marking CK BA121 Marking Code TI OMAP micron marking code information marking code micron label
    Contextual Info: Preliminary‡ 168-Ball x32 Mobile LPDDR PoP TI OMAP Addendum Features Mobile LPDDR Addendum 168-Ball Package-on-Package (PoP) WFBGA TI OMAP MT46HxxxMxxL2KQ Features Options • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS)


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    168-ballmt46hxxxmxxl2kq09005aef83a3b4e1/source09005aef83a3b4cb+10csn-11mt46h64m32l2kq168bmicron lpddrlpddrsmd code marking ckba121marking code ti omapmicron marking code informationmarking code micron label PDF

    Contextual Info: 64M32V1-XSBX 64M32V1-XSBX *ADVANCED 512MB 2 x 64M x 32 / 1GB (4 x 64M x 32) NOR Flash Multi-Chip Package 3V Page Mode Memory FEATURES GENERAL DESCRIPTION  Single power supply operation The 64M32V1-XSBX device is a 3V single power flash memory and utilizes four chips organized as 67,108,864 words. The


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    w7264m32v1-xsbxw7464m32v1-xsbx512mb32-bit+216-bit1024-byte PDF

    Contextual Info: 64M32V1-XBX 256MB – 64Mx32 NOR Flash Multi-Chip Package 3V Page Mode Memory FEATURES GENERAL DESCRIPTION  Single power supply operation The 64M32V1-XBX device is a 3V single power flash memory. The device utilizes two chips organized as 67,108,864 words. The


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    w764m32v1-xbx256mb64mx3232-bit+316-bit1024-bytefo2013 PDF

    Contextual Info: White Electronic Designs 64M32V-XSBX 64Mx32 Flash Multi-Chip Package 3.0V Page Mode Flash Memory FEATURES  Software features  Single power supply operation • Program Suspend and Resume: read other sectors before programming operation is completed


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    64mx32128-word/256-byte8-word/16-byte64-bit PDF

    Contextual Info: White Electronic Designs 64M32V-XSBX PRELIMINARY* 64Mx32 Flash Multi-Chip Package 3.0V Page Mode Flash Memory FEATURES Single power supply operation Software features • 3 volt read, erase, and program operations • Program Suspend and Resume: read other


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    64mx32128-word/256-byte8-word/16-byte64-bit PDF

    lpddr2 256mb

    Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2
    Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ


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    256mbnt6dm16m16adnt6dm8m32ac-16meg+816m16lpddr2 256mbnt6dm8m32ac-t1lpddr2 layoutnt6dm8m32dual lpddr2lpddr2 256mb kgdlpddr2-s2 PDF

    Contextual Info: Preliminary‡ 2Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks 64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 - 32 Meg x 16 x 4 Banks x 4


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    mt46h128m16lfmt46h64m32lfmt46h128m32l2mt46h256m32l4+4mt46h256m32r460-ball90-ball09005aef84e25f2e PDF

    lpddr2 DQ calibration

    Abstract: micron lpddr2 lpddr2-s4 ADQ28 MT42L128M16D1 LPDDR2 SDRAM micron MT42L64M32D1 MT42L128M32D2 mt42l256m32 LPDDR2 1Gb Memory
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L128M16D1, 64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features Options • VDD2: 1.2V • Configuration – 16 Meg x 16 x 8 banks x 1 die


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    mt42l128m16d1mt42l64m32d1mt42l64m64d2mt42l128m32d2+12mt42l256m32d4mt42l128m64d4mt42l96m64d3mt42l192m32d309005aef83f3f2eblpddr2 dq calibrationmicron lpddr2lpddr2-s4adq28lpddr2 sdram micronmt42l256m32lpddr2 1gb memory PDF

    F012

    Abstract: MT46H128M16 Dual LPDDR2 ELPIDA mobile dram LPDDR2 MT46H128 MT46H64M32LF MT46H128M
    Contextual Info: 2Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks 64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 - 32 Meg x 16 x 4 Banks x 4


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    mt46h128m16lfmt46h64m32lfmt46h128m32l2mt46h256m32l4+8mt46h256m32r409005aef8457b3ebf012mt46h128m16dual lpddr2elpida mobile dram lpddr2mt46h128mt46h128m PDF

    MT46H128M32L2

    Abstract: ELPIDA DDR User
    Contextual Info: Preliminary‡ 2Gb: x16, x32 Automotive Mobile LPDDR SDRAM Features Automotive Mobile LPDDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks 64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4


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    mt46h128m16lfmt46h64m32lfmt46h128m32l2mt46h256m32l4+3mt46h256m32r409005aef84e25f2eelpida ddr user PDF

    Contextual Info: White Electronic Designs 64M32V-XSBX ADVANCED* 64Mx32 Flash Multi-Chip Package 3.0V Page Mode Flash Memory FEATURES Single power supply operation Software features • 3 volt read, erase, and program operations • Program Suspend and Resume: read other


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    w764m32v-xsbx64mx32128-word/256-byte PDF

    MT46H64M32

    Abstract: MT46H128 MT46H64M32L2CG-6 MT46H128M 152-Ball lpddr MT46H128M32 micron lpddr 128M32 MT46H128M32L4KZ
    Contextual Info: 152-Ball x32 Mobile LPDDR only PoP (TI-OMAP) Features Mobile LPDDR (only) 152-Ball Package-on-Package (PoP) TI-OMAP MT46HxxxMxxLxCG MT46HxxxMxxLxKZ Features Options • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR)


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    152-ballmt46hxxxmxxlxcgmt46hxxxmxxlxkz09005aef833913f1/source+1009005aef833913d6mt46h64m32mt46h128mt46h64m32l2cg-6mt46h128mlpddrmt46h128m32micron lpddr128m32mt46h128m32l4kz PDF

    smd marking K23

    Abstract: lpddr SMD transistor MARKING CODE g23 marking k22 SMD 168-ball LPDDR sac105 LPDDR Pop smd transistor ab2 MT46H64M32 SMD transistor k23
    Contextual Info: Preliminary‡ 168-Ball x16, x32 Mobile LPDDR PoP TI OMAP Mobile DDR SDRAM Addendum Mobile LPDDR 168-Ball Package-on-Package (PoP) TI OMAP MT46HxxxMxxLxJG Features Options • Vdd/Vddq = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS)


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    168-ballmt46hxxxmxxlxjg09005aef833508fb/source09005aef83350d72+10smd marking k23lpddrsmd transistor marking code g23marking k22 smd168-ball lpddrsac105lpddr popsmd transistor ab2mt46h64m32smd transistor k23 PDF