I960SX Search Results

Contextual Info: ÿ y : V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401 Gx processors • High-perform ance burst DRAM controller • Two-channel fly-by DMA controller • Serial com m unications unit

heartbeat counter

Abstract: PPC401GF V960PBC V961PBC V96SSC V96SSC-33LP AD1065 ppc401
Contextual Info: V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960Sx/Jx AND PowerPC 401Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • System watchdog and heartbeat timers • 16 general purpose I/O bits

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

I960SX

Abstract: V96SSC
Contextual Info: V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Jx/Sx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Glueless interface between Intel’s i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices Fast time-to-market • Support for boot PROM devices

AD11

Abstract: AD12 AD14 AD30 V960PBC V960PBC-33 V961PBC V96SSC 160-Pin Flat Package pci bridge sda 4211
Contextual Info: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR i960Sx PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Sx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local

Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

I960JX v363epc

Abstract: 160-Pin Flat Package pci bridge V380SDC
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

PAL20V8

Abstract: BRY 56 C MACHXL AMD pal20v8 DRAM controller EPX780 rick jd MACH210 BRY 56 B Intel AP-726
Contextual Info: A AP-726 APPLICATION NOTE Interfacing the i960 Jx Microprocessor to the NEC µPD98401* Local ATM Segmentation and Reassembly SAR Chip Rick Harris SPG 80960 Applications Engineer Intel Corporation Semiconductor Products Group Mail Stop CH6-311 5000 W. Chandler Blvd.

Contextual Info: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR ¡960 Sx PROCESSORS • Glueless interface between Intel ¡960Sx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation • Up to 1 Kbyte burst access support on both local

V363EPC-50LP

Abstract: V380SDC LA5-80V102MS21 B LA18 code I960JX I960JX v363epc LAD12
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

I960CX

Abstract: I960 hx eeprom 1011 I960JX
Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

i960J

Contextual Info: V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS Glueless interface to Intel’s ¡960Jx and IBM’s PowerPC 401 Gx processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion

96 pin DIN connector

Abstract: pci schematics I960SX MON960 Quatro-960
Contextual Info: SUPPORT COMPONENTS V3 CORPORATION Quatro-960 PCI Add-In Card Evaluation Platform • ■ ■ ■ ■ ■ ■ ■ ■ ■ Reconfigurable to Allow Benchmarking of i960 Processors Up to 40 MHz Local Bus Operation Uses V3 Corporation’s V96xPBC i960 CPU-to-PCI Bridge Controller

10B5

Abstract: 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960 hx
Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

6SS4

Abstract: LA 7681 LA01 9060SD I960CX PCI9060SD Pgti
Contextual Info: T E C H N D L U PCI 9060SD E Y A November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

V360EPC

Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-performance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

I960SX

Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

iso 4903

Abstract: 9060SD I960CX PCI9060SD
Contextual Info: PCI 9060SD T E C H N D L Q B Y MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters Feat u res_ General Description _ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

10B5

Abstract: 93C06 93CS56 I960CX NM93CS06 NM93CS46 PCI9060SD I960JX
Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _