V350EPC Search Results

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

Contextual Info: V350EPC Rev A0 ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Applications BLOCK DIAGRAM • Glueless interface to Intel’s i960 Jx and IBM PowerPC 401Gx processors • I2O ATU and messaging unit including hardware controlled circular queues

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

i960J

Contextual Info: V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS Glueless interface to Intel’s ¡960Jx and IBM’s PowerPC 401 Gx processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion

I960SX

Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

STKK

Abstract: tvp ul 137 AD12 AD14 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V‘ 5f V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS &M|£ 0 * 1Glueless ¡960Jx/Sx processors interface l20 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture

Contextual Info: v* * -m am # if A V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS T „v * '« IC O * 1Glueless ¡960Jx/Sx processors interface 1120 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture

I960JX v363epc

Abstract: 160-Pin Flat Package pci bridge V380SDC
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

V363EPC-50LP

Abstract: V380SDC LA5-80V102MS21 B LA18 code I960JX I960JX v363epc LAD12
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

V360EPC

Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-performance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

intel DMA controller Unit

Abstract: AV96JA0330420 V350EPC V96SSC V96SSC-33LPB1 A3126
Contextual Info: V96SSC HIGH INTEGRATION SYSTEM CONTROLLER For i960 Jx/Sx and PowerPC 401 Gx Processors Glueless interface between Intel® i960® Jx/Sx series and IBM® PowerPC 401™ Gx processors, DRAM arrays, and peripheral devices Local bus speeds up to 33 MHz High performance burst DRAM

fast page mode dram controller

Abstract: V350EPC V360EPC V363EPC V96BMC V96BMC-33LPD V96BMC-40LPD IBM "embedded dram" 250 mhz IBM PowerPC Processor
Contextual Info: V96BMC HIGH PERFORMANCE BURST DRAM CONTROLLER For Intel i960® Cx/Hx/Jx and IBM® PowerPC 401 Gx Processors Direct interface to Intel® i960® Cx/Hx/Jx and IBM® PowerPC 401™ Gx processors Achieves SRAM performance using DRAM Supports up to 512 Mbytes of DRAM

V380SDC

Abstract: ibm rev 3.3 pinouts LAD11 V3 Semiconductor V360EPC DS-EC301-0101 LAD-22 V363EPC AD30 V350EPC
Contextual Info: V363EPC A0 Data Sheet V363EPC A0 Local Bus to PCI Bridge for Embedded Processors 1.0 About the V363EPC ▼ I2O-Ready ATU and messaging unit, including hardware controlled circular queues ▼ Direct interface to these processors: • AMD AM29030/40™

Contextual Info: UM-SD01-0101.book Page 1 Saturday, November 4, 2000 2:44 PM V380SDC HIGH PERFORMANCE SDRAM CONTROLLER User’s Manual UM-SD01-0101.book Page 2 Saturday, November 4, 2000 2:44 PM 2 0 0 0 by V 3 S em ic o n d u c t o r Co r p. The Em b e d d e d I n t e l l i g e n c e Co m p a n y  i s a t r a d e m a r k o f V 3 S em ic o n d u c t o r Co r p o r a t i o n .

powerpc 403gcx

Abstract: 403GCX V380SDC i960Cx Instruction Set Quick Reference V360EPC 79RC32364 MC68040 MCF5102 MCF5202 MPC750
Contextual Info: Application Note Interfacing PowerPC 403GCX to the V380SDC SDRAM Controller 1.0 Objective This application note describes how to interface the IBM PowerPC 403GCX RISC controller to the V380SDC SDRAM controller. Throughout this document, references are made to the operation of the PowerPC 403GCX and