960JX Search Results

Contextual Info: Advance Data Sheet September 1996 m icroelectronics group Lucent Technologies Bell Labs Inrxsvatians 960JX Embedded 32-Bit RISC Processor Features • Functionally equivalent to Inters 80960JA/JF embedded 32-bit microprocessor ■ High-performance embedded architecture

Contextual Info: Product Brief May 1997 960JX Embedded 32-Bit RISC Processor Features • Functionally equivalent to Intel ’s 80960JA/JF embedded 32-bit microprocessor ■ High-performance embedded architecture ■ High-speed interrupt controller ■ Two on-chip timers ■

24CO8

Abstract: a19t transistor 24co4 IC circuit diagram pin configurations of 24co4 1 24co4 S5933QE Sandy Bridge eeprom 24co2 24CO2 CSI 24C04
Contextual Info: A PPLIED M ICRO C IRCUITS C ORPORATION PCI PRODUCTS DATA BOOK For Marketing and Application Information Contact: Please refer to AMCC’s website at www.amcc.com for the latest Device Summary information for the S5920 and S5933 PCI products. Applied Micro Circuits Corporation

LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local

a19t

Abstract: A18T 92121 0011 amcc s5933 pci controller amcc S5933 1996 a12t A11t 92121 001 A8-15 S5933
Contextual Info: APPLICATION NOTE 1.0 ADD-ON DMA CONTROLLER DESIGN FOR THE S5933 ADD-ON DMA CONTROLLER DESIGN FOR THE S5933 INTRODUCTION The S5933 allows PCI bus master transfers through the FIFO interface. The function of filling and emptying the FIFO is left to add-on logic. Many add-on designs implement a microprocessor or microcontroller with an integrated DMA

Contextual Info: .«artHEH » .¿•■■■I_ im ara« IM I 1 WIMIBII Galileo Technology, System Controller For ¡960JX Processors FEATURES Integrated system controller for embedded applica­ tions Supports the ¡960JX family of CPUs 16-33MHz bus frequency Flexible DRAM controller

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

js83

Abstract: 28f040 JS98 edo dram 72-pin simms 64mb JS108 JS-105 74LS373SC JS31-JS32 JS107 BYU25
Contextual Info: 32-bit 960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Flexible evaluation, benchmark, software, and hardware development system for the GT-32090 System

Contextual Info: GT-96010 Remote Access Coprocessor Product Pre vie w Revision 0.59 i.p. 5/28/97 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES Integrated serial communications controller and system core logic device - Direct interface to i960 Jx family of CPUs

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

i960J

Contextual Info: V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS Glueless interface to Intel’s ¡960Jx and IBM’s PowerPC 401 Gx processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion

amcc s5933

Abstract: amcc pci matchmaker amcc pci matchmaker S5933 S5933
Contextual Info: 80 TEP PACKAGE PINOUT APPLICATION BRIEF S5933 PCI MATCHMAKER — INTERFACING THE INTEL i960 Jx TO THE PCI BUS S5933 PCI MATCHMAKER — INTERFACING THE INTEL i960® Jx TO THE PCI BUS 1.0 AMCC S5933 PCI MATCHMAKER ARCHITECTURE 1.1.1 The best solution for interfacing to the PCI bus is an

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

V360EPC

Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-performance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

4M64

Abstract: "Spanning Tree" BUT15
Contextual Info: Galaxy Family Devices lia lile o G T-48212 / G T-48208 / GT-48207 Advanced Switched Ethernet Controllersfor 10+10/100 BaseX for 10OBaseX Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Single-chip Switched Ethernet Controllers for 10 and

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

PPC401

Abstract: MAS 10 RCD V3 SEMICONDUCTOR I960SA V96SSC AV9154-04
Contextual Info: Chapter 1 Introduction to the V96SSC The V96SSC High-lntegration System Controller provides many of the common peripheral functions required to build a high-performance ¡960 Sx or ¡960Jx processor based system in one low-cost component. The V96SSC coupled with DRAM, ROM, and one of Intel’s

Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-perform ance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

Contextual Info: M H I H Galileo "SmsI Technology, Inc. » System Controller GT- 32090 For ¡960JX Processors _ , . _ Preliminary, Rev. 2.0 FEATURES Integrated system controller for embedded applica­ tions Supports the ¡960JX family of CPUs 16-33MHz bus frequency Flexible DRAM controller

Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation

STKK

Abstract: tvp ul 137 AD12 AD14 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V‘ 5f V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS &M|£ 0 * 1Glueless ¡960Jx/Sx processors interface l20 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture

24CO8

Abstract: 24co4 IC circuit diagram pin configurations of 24co4 1 SAYB S5933DK 24co4 A19T pic 92121 S5933DK1 Accord Technologies
Contextual Info: A PPLIED M ICRO C IRCUITS C ORPORATION S5933 PCI CONTROLLER DATA BOOK For Marketing and Application Information Contact: Applied Micro Circuits Corporation 6290 Sequence Drive San Diego, CA 92121-4358 800 755-2622 (619) 450-9333 Fax (619) 450-9885 http://www.amcc.com

green hills ppc compiler manual

Abstract: pragma ghs startdata green hills compiler user manual green hills ppc linker manual green hills compiler option green hills compiler manual v850 green hills ada compiler user manual green hills compiler GHS linker porting green hills compiler manual
Contextual Info: Green Hills C User’s Guide Version 1.8.9 Copyright 1983-1999 by Green Hills Software, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording,

Contextual Info: v* * -m am # if A V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS T „v * '« IC O * 1Glueless ¡960Jx/Sx processors interface 1120 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture