I960CX Search Results

i960Cx

Abstract: AA10 V96BMC V96BMC-33LP V96BMC-40LP
Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to i960Cx/Hx/Jx processors. • Integrated Page Cache Management.

Contextual Info: V360EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface to i960Cx/Hx and AMD29030/40 processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Signal Path Designer

Contextual Info: V96BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960 Cx/Hx/Jx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Direct interface to i960Cx/Hx/Jx processors • 2Kbyte burst transaction support • SRAM performance achieved with DRAM • Designed to work with V961PBC and

i960Cx

Abstract: V360EPC AD30 V292PBC V360EPC-33 V360EPC-50 V962PBC V96BMC
Contextual Info: V360EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface to i960Cx/Hx and AMD29030/40 processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to i960Cx/Hx/Jx processors. • Integrated Page Cache Management.

LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local

Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

I960JX v363epc

Abstract: 160-Pin Flat Package pci bridge V380SDC
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

PPC401GF

Abstract: V292PBC V960PBC V960PBC-33 V961PBC V961PBC-33 V961PBC-40 V962PBC V962PBC-33 V962PBC-40
Contextual Info: VxxxPBC Rev. B2 LOCAL BUS TO PCI BRIDGE CONTROLLERS Data Sheet Addendum • I2OTM ready hardware messaging unit • Large, 576-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION architecture • 2 channel DMA controller • 33MHz and 40MHz local bus versions available

Contextual Info: PCI 9030 Data Book PCI 9030 Data Book Version 1.1 January 2001 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 408 774-2169 Fax:  2001 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

29035

Abstract: AHA3410C AHA3410C-025 AHA3411 AHA3422 AHA3431 MO-108 68XXX
Contextual Info: Product Specification AHA3410C StarLiteTM 25 MBytes/sec Simultaneous Lossless Data Compression/Decompression Coprocessor IC 2365 NE Hopkins Court Pullman, WA 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advancedhardwarearchitectures

AD12

Abstract: AD14 AD30 V292PBC V962PBC V962PBC-33 V962PBC-40 V96BMC
Contextual Info: V962PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960 Cx/Hx processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

GT-48212

Abstract: TC3001 IC TC3001 "filtering database" GT-48208 GT-64010A GT-64120 Motorola ColdFire 5202 led matrix 16X32 intel 80486 pin diagram
Contextual Info: GT-48212 Advanced Switched Fast Ethernet Controller for 10+10/100 BaseX Preliminary Revision 1.0 March 4, 1998 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Single-chip Switched Ethernet Controller for 10 and

computer networking lan diagram

Abstract: GT-96010 multiple channel router i486sx Galileo 24 ports plx 9050 i960RP Intel Galileo
Contextual Info: alileo GT-96010 Remote Access Coprocessor Technology Backgrounder May 1997 Galileo Technology GT-96010 Technology Backgrounder GT-96010 Technology Backgrounder Searching for Flexibility in Remote/WAN-Access System Design Although integrated silicon solutions have simplified the design of LAN/WAN products such as Internet

fast sram 200mhz 8k

Abstract: KS32C50100 ARM10TDMI block diagram ARM7 set associative ARM10TDMI ARM920T 1997 KS* I2C UART buffer ic KS32C5000A 196QFP
Contextual Info: Rev. 1.8 W - Network Business KS32C5000A 32-bit RISC Microcontroller for Networking Dec. 1998 Network Group , SYSTEM LSI ELECTRONICS December ‘98 Network Team CPU Roadmap KS32C5000A 1996 1997 1998 • 150 ~ 200MHz ARM9TDMI • 0.35/0.25um TLM • 1.0mA/MHz@2.5V

Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR ¡960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to ¡960Cx/Hx/Jx processors. • Integrated Page Cache Management.

AHA3410C

Abstract: AHA3430 AHA3430A-040 IDT3081 R3000
Contextual Info: comtech aha corporation Product Specification AHA3430 StarLite 40 MBytes/sec Simultaneous Compressor/Decompressor IC, 3.3V – 120 Pin PS3430_0101 A subsidiary of Comtech Telecommunications Corporation 2345 NE Hopkins Court Pullman WA 99163 tel: 509.334.1000

plx 9030 176-pin pqfp

Abstract: plx 9052
Contextual Info: PCI 9030 Data Book Version 1.0 April 2000 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 408 774-2169 Fax:  2000 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may

V363EPC-50LP

Abstract: V380SDC LA5-80V102MS21 B LA18 code I960JX I960JX v363epc LAD12
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

I960CX

Abstract: I960 hx eeprom 1011 I960JX
Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

doorbell application

Abstract: la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132