HDLC Search Results

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* HDLC Protocol Controller Features • MT8952B _ ISSUE 5_May 1995 Formats data as per X.25 CCITT level-2 standards Ordering Information MT8952BC 28 Pin Ceramic DIP MT8952BE 28 Pin Plastic DIP

cd 4553

Abstract: ic cd 4553 cmos 4553 ATM machine working circuit diagram GPON block diagram ic 4553 master 5087 mii to hdlc DS34S101 DS34S102
Contextual Info: ABRIDGED DATA SHEET Rev: 101708 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial

siemens 82525

Abstract: SAB 82258 SAF 82526 N V2.2 siemens serial modem tsa siemens Q67100-H6504 SAB82520 siemens 8051 microcontroller saf82525 SAB82525N
Contextual Info: SAB SAB SAF SAF SIEMENS High-Level Serial Communications Controller Extended HSCX Preliminary Data 1 82525 82526 82525 82526 CMOS 1C Features Serial Interface • Two independent full-duplex HDLC channels (SAB 82526: one channel) - On chip clock generation or external clock source

Contextual Info: 05015 Only One Name Means ProTek’Tion VSIP SERIES A & B VSIP® TVS ARRAY APPLICATIONS ✔ RS-232 and RS-423 Data Lines ✔ Telecommunications T/R Protection: ISDN, ADSL, V.34/V.90, HDLC, T1/E1 & T3/E3 ✔ Low & High Speed Data Lines: Ethernet &Token Ring

hdlc

Abstract: MC92460 MPC8260 OC192 OC48
Contextual Info: Advance Information Rev. 1, 1/2002 MC92460 HDLC Controller Technical Summary The MC92460 is a 40-channel, high-level data link controller HDLC with an aggregate throughput of up to 2.0 Gbps across a synchronous optical network (SONET). A total of eight of these peripheral devices can be connected to the 60x bus of the MPC8260 or the MPC603e.

multiplexing e1 frame to e3 frame

Abstract: S1215P S1215 STM MARKING GR-253 TU12 32xDS1
Contextual Info: Product Brief 5 21 S1 UR AM S1215 Amur Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH Line Features Tributary Features S1215 (Amur) interfaces with 155Mbps/622Mbps SONET/SDH (1xSTS-12/STM-4, 4xSTS-3/STM-1)

UPS SIEMENS

Abstract: SMD IC MARKING GP a1s smd AD211 as3 SMD Transistor siemens sab 82532 transistor SMD MARKING CODE nx smd transistor marking a2h smd marking ARB b32 siemens
Contextual Info: S IE M E N S ICs for Communications Multichannel Network Interface Controller for HDLC with Extensions MUNICH32X PEB 20321 Version 2.1 Preliminary Data Sheet 01.98 DS 1 This Material Copyrighted By Its Respective Manufacturer Edition 1998-01-23 This edition was realized using the software

Z8000

Abstract: z8530 8086 logic diagram dc av converter Z8030 8086 interrupt structure 8086 structure interrupt structure of 8086 CRC-16 Z-636
Contextual Info: Z8030/Z8530 Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Programmable Synchronous Modes - SDLC and HDLC, and SOLC loop supported with frame control, zero insertion and deletion, abort, a residue handling - CRC-16 and CCITT generators and checkers

RFC-1331

Abstract: 105GT-2 80X86 CL-CD2401 CL-CD2431 gt22a iso 3309
Contextual Info: CL-CD2430/CD2431 DataBook i "CIRRUS LOGIC FEATURES • Intelligent 4-Channel Local and WAN Communications Controller Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link

Contextual Info: NOV 3 t Î99I ! Preliminary Advanced Micro Devices Am2075 ISDN Digital Exchange Controller IDEC DISTINCTIVE CHARACTERISTICS • Four independent HDLC channels ■ 64-byte FIFO storage per channel and Programmable time slots and channel data rates (up to 4 Mb/s)

AM82520

Abstract: AM82520B
Contextual Info: Preliminary S Am82520 High-Level Serial Communications Controller HSCC Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Two independent HDLC channels Telecom-specific features programmable Implementation ot X.25 LAPB/LAPD protocol 8-bit parallel |iP interface

Contextual Info: l ’n .'iim iru iy Advanced Micro Devices Am82520 HSCC High-Level Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Two Independent HDLC channels ■ Telecom-specific features programmable ■ Implementation of X.25 LAPB/LAPD protocol ■ 8-bit parallel microprocessor interface

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

SMD transistor 6c

Abstract: siemens ecu marking code B9 DG SMD Transistor nat4 smd CHN 842 marking BARX A23i as3 SMD Transistor CHN 841 marking code E3 SMD ic
Contextual Info: S IE M E N S ICs for Communications Multichannel Extensions MUNICH32X Network Interface Controller for HDLC with PEB 20321 Version 1.1 Preliminary Data Sheet 10.96 T 20 32 -1 V 11 -D1 -7600 This Material Copyrighted By Its Respective Manufacturer Edition 10.96

stk 412 -410

Abstract: stk 412 -420 stk 432 070 MM5823 STK 412 240 CIR 2262 cir 2262 af stk 412 -230 hiab STk 412 120
Contextual Info: S lB b b B R DDOtilS4 “i2 ñ m C I R wm. C L -C D 2 4 0 0 /C D 2401 •SK-H CIRRUS LOGIC Data Book FEATURES Four-Channel, Multi-Protocol Communications Controller General • Four full-duplex channels ■ All channels support async, blsync, HDLC/ SDLC, and X.21 programmable sync protocols

HSCX 82525

Abstract: R8051XC-HDLC hdlc R8051XC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

hdlc

Abstract: GR-253 P802 S19205 S19205CBI S3091 S3092
Contextual Info: KHATANGA Product Brief Part Number S19205CBI, Revision 1.4, October 2002 10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper Features • POS processing includes HDLC framing, payload scrambling x43 + 1 and transparency processing. • Single STS-192c/STM-64 framer/mapper device to support 10

CRC-32

Abstract: FREEDM-32P672 GPIC672 PM7380 RHDL672 PM4314
Contextual Info: PMC-Sierra,Inc. Preliminary PM7380 FREEDM-32P672 Frame Engine and Data Link Manager FEATURES The FREEDM32P672 chip offers the following features: • Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect PCI 2.1 compliant bus for

CRC-32

Abstract: pm8315 FREEDM-84P672 GPIC672 M66EN PM7384 RHDL672 Multi-Channel hdlc Controller
Contextual Info: PMC-Sierra,Inc. PM7384 FREEDM-84P672 Preliminary Frame Engine and Data Link Manager FEATURES • Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit PCI 2.1 compliant bus for configuration, monitoring and transfer of packet data. • On-chip DMA controller with scatter/

hfc-s

Abstract: VAC L5051-X014-80 L5051-X014-80 l5051-x014 l5051 vogt 543 vogt f6 vogt 1N4148 PCM30
Contextual Info: DATA SHEET HFC - S 2BDS0 ISDN HDLC FIFO controller with S/T interface Copyright 1994 - 1997 Cologne Chip Designs All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by

PEB3265

Abstract: PEB4266 DUSLIC application notes PEB4266 PEB2091 C165H C166 PEB82902 PEB82912
Contextual Info: Product Brief The C165H is a new low-cost member of the Infineon Communication Controller family. The device combines the successful Infineon C166 16-bit full static core with four independent HDLC controllers, IOM -2 interface and 3-KByte of on-chip Dual-Port RAM. The C165H

Contextual Info: 05015 VSIP SERIES A & B . . . engineered solutions for the transient environment VSIP® TVS DIODE ARRAY APPLICATIONS ✔ RS-232, and RS-423 Data Lines ✔ Telecommunications T/R Protection: ISDN, ADSL, V.34/V90, HDLC, T1/E1 and T3/E3 ✔ Low and High Speed Data Lines: Ethernet, Token Ring, USB, and Fire Wire

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter