RNEG2 Search Results

rneg2

Abstract: CON8AP TG08-1505N1 CON2AP rneg4 con3 81L27 XRT81L27 3r18 con8a
Contextual Info: A B C D E TP3 3.3v 1 VCC3v3 TP1 J9 2 + L1 FB 1 + 1 1 C5 0.1uF C6 0.1uF C7 0.1uF D2 LED DVDD DVDD DVDD 1 2 1 GND J1 RCLK1 RPOS1 RNEG1 2 4 1 3 5 7 + + + + 2 4 6 8 + + + + 120 119 118 RCLK1 RPOS1 RNEG1 CON8AP J2 RCLK2 RPOS2 RNEG2 1 3 5 7 VCC3v3 R39 SRST 4.7k

DF2-A

Abstract: XB2H DF2E
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte wide drop and add buses

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

CON12

Abstract: kx-7 26 SO-64 CS61582 CS61582-IQ5 CS61584 12.352 cts
Contextual Info: CS61582 A Cirrus Logic Company D ual T1/E1 Line Interface Features General Description • The CS61582 is a dual line interface optimized for highly-integrated T1/E1 asynchronous or synchronous multiplexer applications such as SONET and SDH. Each channel features individual control and status

300 Amp mosfet

Contextual Info: UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier Check for Samples: UCD7230 FEATURES APPLICATIONS • • 1 2 • • • • • • •

IR DATABOOK SCR

Abstract: cmos logic databook BTS 8800 COMCLOK 13.56 CON12 line output transformer for television Transformer te-e TTL databook TTL databook application CS61584A
Contextual Info: CS61584A Product Databook =CIRRUS LOGIC FEATURES • Dual T1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions D ual T1/E1 Line In terface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications ■ Matched Impedance Transmit Drivers

CX28331

Abstract: CX28332 CX28333 TBR24 48-ETQFP AMI 52 732 V
Contextual Info: Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit Data Sheet CX28331/CX28332/CX28333 –3x 28333-DSH-002-B Feb 2003 Revision History Revision Level Date Description A — 6/2001 Initial Release [Document number 28333-DSH-002-A] B — 2/2003 Removed CX2833i-1x information (see separate document)

TR62411

Abstract: DS2141A DS21Q41B DS21Q41BTN TR54016
Contextual Info: DS21Q41B Quad T1 Framer www.dalsemi.com FEATURES § § § § § § § § § § § § § § § § Four T1 DS1/ISDN-PRI framing transceivers All four framers are fully independent Frames to D4, ESF, and SLC-96 formats 8-bit parallel control port that can be

Contextual Info:  XRT7302 PRELIMINARY 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 1999 REV. 1.0.0 GENERAL DESCRIPTION APPLICATIONS The XRT7302 Dual Channel E3/DS3/STS-1 Transceiver IC consists of two fully integrated transmitter and receiver line transceiver blocks that are designed

Contextual Info: áç XRT71D04 PRELIMINARY 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D04 is a four channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore

Contextual Info:  XRT81L27 PRELIMINARY SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY OCTOBER 2000 REV. P1.0.1 GENERAL DESCRIPTION The XRT81L27 is an optimized seven-channel, analog, 3.3V, line interface unit, fabricated using low power CMOS technology. The device contains seven

dmo 365 r

Abstract: dmo 365 XRT83VSH316IB-F
Contextual Info: XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT OCTOBER 2007 REV. 1.0.0 GENERAL DESCRIPTION for external timing 8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1 . The XRT83VSH316 is a fully integrated 16-channel short-haul line interface unit (LIU) that operates from

Contextual Info: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,

Contextual Info: DS21Q41B PRELIMINARY DALLAS DS21Q41B Q u a d T I Framer SEMICONDUCTOR FEATURES FUNCTIONAL DIAGRAM • F o u rU DS1/ISDN-PRI framing transceivers • All four framers are fully independent • Frames to D4, ESF, and SLC-96 formats • 8 -b it parallel control port that can be connected to

Contextual Info: CS61582 A Cirrus Logic Company Dual T1/E1 Line Interface Features General Description CS61582 is a dual line interface optimized for Dual T1/E1 Line Interface Optimized for The highly-integrated T1/E1 asynchronous or synchronous Mutiplexer Applications multiplexer applications such as SONET and SDH.

M28335-13P

Abstract: M28335 ferrite RM6 CX28365 M28335EBGC TBR24 DIMENSIONAL STANDARD AH31 AK20 ferrite e16 ferrite transformer ch9i
Contextual Info: Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. M28335 Twelve Port T3/E3/STS-1 Line Interface Unit The M28335 is a 12-channel, T3/E3/STS-1 Line Interface Unit LIU . It is configured via a

Contextual Info: DATA S H E E T JULY 1999 Revision 1.1 LXT384 Octal T1/E1 Transceiver General Description The LXT384 is an octal short haul Pulse Code Modulation PCM transceiver for use in both 1.544 Mbps (Tl) and 2.048 Mbps (El) applications. It incorporates eight independent receivers and eight independent transmitters

68-bga

Abstract: C4 to BGA 144L CDB61881 CS61881 CS61881-IB CS61881-IQ scr 106 C
Contextual Info: CS61881 Octal E1 Analog Front End Features Description • Octal E1 Line Interface Unit Compliant with G.703 The CS61881contains eight analog front ends that each provide the line interface for E1 transmission systems. The device contains eight receivers and transmitters

PRM 231 e1

Abstract: TR-TSY-499 SAS controller chip H100 IXF3208 LXT3008 LXT3108 LXT384 SLC96 G964
Contextual Info: IXF3208 Octal T1/E1/J1 Framer with On-Chip PRM Advance Information Datasheet The Intel IXF3208 with On Chip PRM is an octal framer for T1/E1/J1 and ISDN primary rate interfaces operating at 1.544 Mbps or 2.048 Mbps. Each framer consists of a receive and

Contextual Info: DS21448 3.3V E1/T1/J1 Quad Line Interface www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21448 is a quad-port E1 or T1 line interface unit LIU for short-haul and long-haul applications. It incorporates four independent transmitters and four independent receivers in a single 144-pin PBGA or

DS2143

Abstract: DS21Q41B DS21Q43A DS21Q43ATN RG802 TS15
Contextual Info: DS21Q43A DS21Q43A Quad E1 Framer FEATURES FUNCTIONAL DIAGRAM • Four E1 CEPT or PCM–30 /ISDN–PRI framing transceivers • All four framers are fully independent; transmit and receive sections of each framer are fully independent RECEIVE FRAMER ELASTIC

RI00P

Contextual Info: CS61582 ACfrrus Logic Company Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface Optimized for Mutiplexer Applications The CS61582 is a dual line interface optimized for highly-integrated T1/E1 asynchronous or synchronous

RDC22

Contextual Info: PRELIMINARY DS21Q42 Enhanced QUAD T1 FRAMER DALLAS SEMICONDUCTOR FEATURES FUNCTIONAL DIAGRAM • Four T1 DS1/ISDN—PRI/J1 framing transceivers • All four framers are fully independent • Each of the four framers contain dual twoframe elastic store slip buffers that can connect

ssr 40ac

Contextual Info: DALLAS SEMICONDUCTOR FEATURES • • • • • • • • • • • • • • • Four E 1 CEPT or PCM-30 /ISDN-PRI framing transceivers All four framers are fully independent; transm it and receive sections of each framer are fully independent Frames to FAS, CAS, CCS, and CRC4