XRT71D03 Search Results

Contextual Info: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,

GR-253

Abstract: TBR24 XRT71D03 XRT71D04
Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER APRIL 2001 REV. 1.1.1 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,

Contextual Info: DATA SHEET Communications DS3/E3 Jitter Attenuator XRT71D03 Three Channel DS3/E3/STS-1 Jitter Attenuator, STS-1 to DS3 Desynchronizer Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit

Contextual Info: DATA SHEET Communications XRT71D04 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package

Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER APRIL 2001 REV. 1.1.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,

GR-253

Abstract: TBR24 XRT71D03 XRT71D03IV XRT71D04 IC 2576 5.0v
Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER SEPTEMBER 2001 REV. 1.1.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,

ANSI T1.105.03B 1997

Contextual Info: DATA SHEET Communications XRT71D03 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package

relay finder t29

Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.

Contextual Info: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER SEPTEMBER 2000 REV. P1.0.1 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR253 standards.

IC 2576 5.0v

Abstract: GR-253 TBR24 XRT71D03 XRT71D03IV XRT71D04 71d0
Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

Contextual Info: áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT73L03, 3-Channel, DS3/E3/STS-1 Line Interface Unit consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.

Contextual Info: XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4 GENERAL DESCRIPTION The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip

r4363

Abstract: CP Clare RELAY dmo 465 IC 404
Contextual Info: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.6 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields

dmo 365 r

Abstract: datasheet relay NAIS 5v 5 pin NAIS Relay 5v bi directional dc motor speed controller NAIS 210 NAIS 210 RELAY 5v relay nais 5 pin data sheet DS3-M13 sha t90 T79 code marking
Contextual Info: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER FEBRUARY 2001 REV. P1.1.7 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields

EXAR XR2209

Abstract: XR16C2850 XR68C681 XR88C192 ST16C650A
Contextual Info: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I Exar Products Alphanumeric Index To access product information and data sheets, click on the part number below. ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552

XR2206 application notes

Abstract: pin diagram of ic xr2206 IC XR2206 XR2206 XR2206 pin details for function generator XR2206 monolithic function generator xr2206 circuit peb1756ae fsk modulation and demodulation using Xr2206 MXP2
Contextual Info: Communications OTN Multi-Service OTN Muxponder/Mapper Ethernet Transport Ethernet over PDH Ethernet over SONET/SDH PDH over SONET/SDH Port Expanders SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR PDH E1 LIUs T1/E1/J1 LIUs BITS Solutions

Contextual Info: XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2003 REV. 1.0.0 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip

dmo 465

Abstract: iC 458 datasheet relay NAIS 5v 5 pin M25-A dmo 365 dmo 365 r NAIS 210 RELAY NAIS Relay 5v DS3-M13 XRT72L56
Contextual Info: áç XRT72L56 PRELIMINARY SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The Microprocessor Interface is used to configure the Framer in different operating modes and monitor the performance of the Framer. The XRT72L56, 6 Channel DS3/E3 Framer is designed to accept “User Data” from the Terminal

NAIS 210 RELAY

Abstract: ic 393 k 4213 0X13 DS3-M13 XRT72L52
Contextual Info: áç XRT72L52 PRELIMINARY TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.

Contextual Info: I ABOUT EXAR I PRODUCTS I INDEX I SALES INFORMATION I INFORMATION REQUEST I SEARCH I HELP I DS3/E3 Product Selector Guide DS3/E3 Products DS3/E3 Line Interfaces Part No. #of Channels Data Rates Clock Recovery Temp Range Operating Power Supply Max Current Package s

Contextual Info: DATA SHEET Communications XRT75L00 Single-Chip Line Interface Unit LIU With Jitter Attenuator (JA) for DS3/E3 Environments Features: Receiver: • On-Chip Clock and Data Recovery Circuit for High-Input Jitter Tolerance • On-Chip B3ZS/HDB3 Encoder/Decoder Can be Disabled or Enabled

DMO 565 R

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - ATM ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

Rx1302

Abstract: r4363 dmo 265
Contextual Info: áç XRT72L50 PRELIMINARY SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.