2348G Search Results

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

AD27

Abstract: AD29 V320USC V320USC-75 AD1485
Contextual Info: DS-UC01-0102.fm Page 1 Wednesday, June 30, 1999 7:30 PM Datasheet V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus

MIPS R7000

Abstract: V340HPC ADB 24 AF 239 R5000 mips RM7000
Contextual Info: DS-HC01-0101.fm Page 1 Wednesday, April 11, 2001 1:29 PM 3UHOLPLQDU\ 'DWD 6KHHW 9+3& $ +LJK ,QWHJUDWLRQ 3&, 6\VWHP &RQWUROOHU WWWWWW IRU ELW 0,36Š 3URFHVVRUV  $ERXW WKH 9+3& ‡ Highly scalable, 64-bit PCI system controller for high performance embedded systems

V320USC

Contextual Info: V320USC HIGH INTEGRATION, LOW COST PCI SYSTEM CONTROLLER For 32 Bit MIPS and SuperH™ Processors ▼ Glueless interface between the popular MIPS™ and SuperH™ processors and the industry standard PCI Bus ▼ Fully compliant with PCI 2.2 specification

Contextual Info: V350EPC Rev A0 ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Applications BLOCK DIAGRAM • Glueless interface to Intel’s i960 Jx and IBM PowerPC 401Gx processors • I2O ATU and messaging unit including hardware controlled circular queues

i960Cx

Abstract: AA10 V96BMC V96BMC-33LP V96BMC-40LP
Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to i960Cx/Hx/Jx processors. • Integrated Page Cache Management.

PPC401GF

Abstract: V292PBC V960PBC V960PBC-33 V961PBC V961PBC-33 V961PBC-40 V962PBC V962PBC-33 V962PBC-40
Contextual Info: VxxxPBC Rev. B2 LOCAL BUS TO PCI BRIDGE CONTROLLERS Data Sheet Addendum • I2OTM ready hardware messaging unit • Large, 576-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION architecture • 2 channel DMA controller • 33MHz and 40MHz local bus versions available

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

PPC403GC

Abstract: V360EPC 403GC ID31 LA25 V292PBC V3 Semiconductor
Contextual Info: Interfacing IBM’s PowerPC 403GC to PCI using V360EPC from V3 Semiconductor 1. Objective This application note describes the interface between PPC403GC processors from IBM and V360EPC Enhanced PCI Controller EPC from V3 Semiconductor. The V360EPC family of

2926B

Abstract: DIMENSIONS PQFP 132
Contextual Info: V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS Pin/Software compatible with earlier V292BMC. Software-configured operational parameters. Direct interfaces to Am29030/40 processors. Integrated Page Cache Management. 3.3V DRAM interface support.

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Contextual Info: V292PBC Rev.B2 LOCAL BUS to PCI BRIDGE CONTROLLER FOR Am29030/40 , M68040/60™, SA-110™ and PowerPC™403Gx/403GCx PROCESSORS ❒ Glueless interface between AMD’s Am29030 and Am29040 processors and the industry standard PCI Bus ❒ Fully compliant with PCI 2.1 specification

Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR ¡960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to ¡960Cx/Hx/Jx processors. • Integrated Page Cache Management.

AM29030

Abstract: M68040
Contextual Info: V292BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 AND M68040/60™ PROCESSORS BLOCK DIAGRAM • Direct interface to Am29030/40 processors • Designed to work with V292PBC/V360EPC PCI bridge • Near SRAM performance achieved with DRAM

amd 29030

Contextual Info: V360EPC Rev A0 ENHANCED PCI BRIDGE CONTROLLER For 32-bit De-Multiplexed Address/Data Applications BLOCK DIAGRAM • Glueless interface to Intel’s i960 Cx/Hx and AMD®29030/40 processors • I2O ATU and messaging unit including hardware controlled circular queues

hurricane

Abstract: V320USC EVALUATION KIT HR52312003220 pci slot pcb layout MH64BT0330011 RM5231 V320USC pci card schematic V320USC-75LP
Contextual Info: Hurricane V320USC EVALUATION KIT with the QED RM5231 MIPS® Processor Features the V320USC PCI System Controller for 32-bit PCI Bus, designed by V3 Semiconductor Supports QED® RM5230™ and RM5231™ processors Fully compliant with PCI Local Bus Specification, Revision 2.2

Contextual Info: W f f g i * « % llr £ V 3 7 0 P D C Rev. AO High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit j, v f »KO * • Fully compliant with PCI 2.2 specification target interface • Hot Swap Ready PICMG Hot Swap Specification • Multiplexed or Non-multiplexed 8-, 16-, or 32-bit

Contextual Info: ÿ y : V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401 Gx processors • High-perform ance burst DRAM controller • Two-channel fly-by DMA controller • Serial com m unications unit

Contextual Info: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.

ld18 st

Abstract: tvp ul 137 AD14 V292PBC V360EPC V360EPC-33 V360EPC-50 V962PBC V96BMC
Contextual Info: V‘ 5f V360EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS &M|£ 0 * 1Glueless ¡960Cx/Hx and AMD29030/40 processors interface 1Large, 640-byte FIFOs using V 3’s unique D y n a m ic B a n d w id t h A l l o c a t io n architecture

intel DMA controller Unit

Abstract: AV96JA0330420 V350EPC V96SSC V96SSC-33LPB1 A3126
Contextual Info: V96SSC HIGH INTEGRATION SYSTEM CONTROLLER For i960 Jx/Sx and PowerPC 401 Gx Processors Glueless interface between Intel® i960® Jx/Sx series and IBM® PowerPC 401™ Gx processors, DRAM arrays, and peripheral devices Local bus speeds up to 33 MHz High performance burst DRAM

V363EPC

Abstract: V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC
Contextual Info: V363EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed/Demultiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface

V370PDC-66LPA0

Abstract: SN00000663211 V370PDC
Contextual Info: V370PDC HIGH PERFORMANCE PCI TARGET INTERFACE with Integrated SDRAM Controller Fully compliant with PCI Local Bus Specification, Revision 2.2 Fully compliant with PCI Bus Power Management Interface Specification, Revision 1.0 Hot Swap Ready implemented

fast page mode dram controller

Abstract: V350EPC V360EPC V363EPC V96BMC V96BMC-33LPD V96BMC-40LPD IBM "embedded dram" 250 mhz IBM PowerPC Processor
Contextual Info: V96BMC HIGH PERFORMANCE BURST DRAM CONTROLLER For Intel i960® Cx/Hx/Jx and IBM® PowerPC 401 Gx Processors Direct interface to Intel® i960® Cx/Hx/Jx and IBM® PowerPC 401™ Gx processors Achieves SRAM performance using DRAM Supports up to 512 Mbytes of DRAM