80960SX Search Results

transistor 778

Abstract: cpu 80960kx printer controller 80960SX Destiny d5001 D8905
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D5001 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 80960Sx, 80960Kx, 80960Jx and 80960Cx Supports Up to 1200 dpi Resolutions Band Processing Requires Less

LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: in tj 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY 28F200BX-T/B, 28F002BX-T/B • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

Contextual Info: in te i 1-MBIT 128K X 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X -T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N -T /2 8 F 0 0 1 B N -B • High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block

Contextual Info: in te l A28F400BX-T/B 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F400BX-T, A28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked Architecture

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

Contextual Info: in te i. 28F200BL-T/B, 28F002BL-T/B 2-MBIT 128K x 16, 256K x 8 LOW POWER BOOT BLOCK FLASH MEMORY FAMILY • Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6V ■ Expanded Temperature Range 20°C to +70°C ■ x8/x16 Input/Output Architecture

28F001

Abstract: intel 28F001BXT
Contextual Info: in t e i, 28F001BX-T/28F001BX-B 1M 128K x 8 CMOS FLASH MEMORY • High Integration Blocked Architecture — One 8KB Boot Block w/Lock Out — Two 4KB Parameter Blocks — One 112KB Main Block ■ 10,000 Erase/Program Cycles Minimum Per Block ■ Simplified Program and Erase

micro instruction set of I960 hx

Abstract: 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960
Contextual Info: Intel i960® Processors i960® Architecture Family Product Highlights • 32-bit register-based RISC core in all processors ■ Code compatibility across entire product line ■ Broad selection of price and performance levels ■ Ideal for networking and imaging

Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _

3165* intel

Abstract: 82360SL intel 80386SL twc np 6001 28f200 tsop intel 28f200bx 28F002BX 28F002BX-B 28F002BX-T 28F200BX
Contextual Info: INTEL CORP HEHORY/PLD/ SbE D • 4fl2bl?b 007bBS3 flTb m i T L Z 0M lF K ß ! ilÄ T 0®If!!] in te l 'T W o 'K V ¿ k 28F200BX-T/B, 28F002BX-T/B 2 MBIT (128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B

Contextual Info: 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B , 28F 002B L-T/B • SRAM-Compatible Write Interface ■ Low Voltage Operation for Very Low Power Portable Applications — VCc - 3.0V-3.6V ■ Automatic Power Savings Feature

k 4431

Contextual Info: in te i 28F200BX-T/B, 28F002BX-T/B 2 MBIT 128K x 16,256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x6/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Very High-Performance Read — 60/80 ns Maximum Access Time

T28F400

Abstract: intel 28F400bx E28F400BX-B60 interfacing of memory devices with 80286 microprocessor 80286 internal architecture 28F004BX-B 28F004BX-T 28F400BX-B 28F400BX-T E28F400BX-T60
Contextual Info: 4-MBIT 256K X 16 512K X 8 BOOT BLOCK FLASH MEMORY FAMILY 28F400BX-T B 28F004BX-T B Y x8 x16 Input Output Architecture 28F400BX-T 28F400BX-B For High Performance and High Integration 16-bit and 32-bit CPUs Y Very High-Performance Read 60 80 120 ns Maximum Access Time

Contextual Info: [» [iS C m Y O !* ] In te l A28F200BX-T/B 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F200BX-T, A28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked

i960CA

Abstract: ka 20885 D 80960 EP80960BB atu-3 FF90FF i960 KA/KB Programmers Reference Manual 80960CF 80960RP IQ80960RP
Contextual Info: Getting Started with the 80960 QUICKval Kit i960 Microprocessor Evaluation Kit Order Number: 632708-005 Revision Revision History Date -001 Original Issue. 12/94 -002 80960Hx and PCI80960DP chapters added. Additional examples for all processors added. 12/95

TSOT1610GP-YB21

Abstract: MARS10G el12n 1724-pin STM-64 AU-AIS TSOT1610G 1724P 0AA00 mars10g T-PRO AW23
Contextual Info: Hardware Design Guide April 2005 MARS10G T-Pro and MARS10G TD-Pro TSOT1610GP/GPD SONET/SDH STS-192/STM-64 Overhead Terminator and Path Processor Overview The MARS10G T-Pro and MARS10G TD-Pro are STS-192/STM-64 overhead generators/terminators and path processors, members of the MARS family

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

sun hold RAS 0610

Abstract: eeprom programmer schematic 24c08 80960KB Programmer Reference manual 270929 KDS crystal 20.000 zilog 4202 IC 24c08 PCI cyclone 3 schematics KDS 4.000 Crystal cpu 80960kx
Contextual Info: i960 Microprocessor User’s Guide for Cyclone and PCI-SDK Evaluation Platforms April 1996 Order Number: 272577-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

v945

Abstract: 80960SA N80960SB W225 80960SB N80960SA S80960SA S80960SB intel DOC n80960
Contextual Info: 80960SA/SB SPECIFICATION UPDATE Release Date: June, 1997 Order Number: 272850-002 The 80960SA/SB may contain design defects or errors known as errata which may cause the 80960SA/SB to deviate from published specifications. Current characterized errata are documented in this Specification Update.

29050

Contextual Info: Ä m K l i 0M 1F® I^Ö M 1Ä ¥D ® M in te l A28F200BX-T/B 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY Automotive a x8/x16 Input/Output Architecture • ■ ■ ■ ■ ■ — A28F200BX-T, A28F200BX-B — For High Performance and High

Contextual Info: Ä E W Ä I M I I O G M f ô K iû Â î r O O M in te i A28F400BX-T/B 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F400BX-T, A28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs