80960CA Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: Wfwl LETT mLrJk HEW PACKARD H P E2432A Intel 80960CA/CF Preprocessor Interface For use with HP logic analyzers The HP E2432A preprocessor interface for the Intel 80960CA/CF is a mechani­ cal and electrical interface between the Intel 80960CA/CF and various HP logic analyzers

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

Non-Pipelined processor

Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining

270710

Abstract: CX041A
Contextual Info: ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

xxnx

Abstract: 1bw 85 271326 intel 27218
Contextual Info: Ä E W Ä K l ! D M F fö ß iflÄ irD © rc ] in te l SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

intel PLD

Contextual Info: INTEL CORP UP/PRPHLS . • i n t g MME D ■ - . MÔSbl75 0101313 5 I ■ ITLl ' p ftg y o m M ? l " P i - 6 - 1^ - 27960CX PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM Pipelined Addressing fo r Optimal Bus Bandwidth on 80960CA — N ext Addressing Overlaps Last Data

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

Contextual Info: 80960JS/JC 3.3 V Microprocessor Advance Information Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JS lx the Bus Clock

Contextual Info: in tj 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY 28F200BX-T/B, 28F002BX-T/B • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

Contextual Info: in te i 1-MBIT 128K X 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X -T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N -T /2 8 F 0 0 1 B N -B • High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block

Contextual Info: in te l A28F400BX-T/B 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F400BX-T, A28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked Architecture

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

Contextual Info: PRELIMINARY in te l 28F002BC 2-MBIT 256K X 8 BOOT BLOCK FLASH MEMORY High Performance Read — 80/120 ns Max Access Time 40 ns Max. Output Enable Time Low Power Consumption — 20 mA Typical Read Current x8-Only Input/Output Architecture — Space-Constrained 8-bit

28F001

Abstract: intel 28F001BXT
Contextual Info: in t e i, 28F001BX-T/28F001BX-B 1M 128K x 8 CMOS FLASH MEMORY • High Integration Blocked Architecture — One 8KB Boot Block w/Lock Out — Two 4KB Parameter Blocks — One 112KB Main Block ■ 10,000 Erase/Program Cycles Minimum Per Block ■ Simplified Program and Erase

micro instruction set of I960 hx

Abstract: 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960
Contextual Info: Intel i960® Processors i960® Architecture Family Product Highlights • 32-bit register-based RISC core in all processors ■ Code compatibility across entire product line ■ Broad selection of price and performance levels ■ Ideal for networking and imaging

Contextual Info: BROOKTREE CORP b3E B • 1^455^5 DDQ7G3T Interface Specification IS-210.15 SMDS C o n tro l and R e a sse m b ly F o r m a tte r Part # UGA-210 M arch, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 6 1 9 -4 5 2 -7 5 8 0

3165* intel

Abstract: 82360SL intel 80386SL twc np 6001 28f200 tsop intel 28f200bx 28F002BX 28F002BX-B 28F002BX-T 28F200BX
Contextual Info: INTEL CORP HEHORY/PLD/ SbE D • 4fl2bl?b 007bBS3 flTb m i T L Z 0M lF K ß ! ilÄ T 0®If!!] in te l 'T W o 'K V ¿ k 28F200BX-T/B, 28F002BX-T/B 2 MBIT (128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B

82371FB

Abstract: 28F002BC 82437fx 36A4
Contextual Info: E n n n n n n PRELIMINARY 28F002BC 2-MBIT 256K X 8 BOOT BLOCK FLASH MEMORY High Performance Read  80/120 ns Max Access Time 40 ns Max. Output Enable Time Low Power Consumption  20 mA Typical Read Current x8-Only Input/Output Architecture  Space-Constrained 8-bit

RC32364

Abstract: 80960CA IDT79RC32364
Contextual Info: Integrated Device Technology, Inc. Achieving Compatibility Between the Intel i960 and the RC32364 Embedded Microprocessor Application Note AN-155 By: Salahuddin Ameer Introduction The IDT79RC32364 is a new low-cost, lowpower member of the Integrated Device Technology, Inc. IDT RISControllerTM series of

Contextual Info: ß R IH L D ß ilD IM D O T r in te i 80960JD EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is 2x the Bus Clock — Load/Store Programming Model

8F004

Contextual Info: in U I v PRELIMINARY 5 VOLT BOOT BLOCK FLASH MEMORY 28F002BC x8 • High Performance Read — 80/120 ns Max. Access Time 40 ns Max. Output Enable Time ■ Extended Cycling Capability — 100,000 Block Erase Cycles ■ Automated Byte Write and Block Erase