80960C Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: Wfwl LETT mLrJk HEW PACKARD H P E2432A Intel 80960CA/CF Preprocessor Interface For use with HP logic analyzers The HP E2432A preprocessor interface for the Intel 80960CA/CF is a mechani­ cal and electrical interface between the Intel 80960CA/CF and various HP logic analyzers

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

Non-Pipelined processor

Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining

270710

Abstract: CX041A
Contextual Info: ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

xxnx

Abstract: 1bw 85 271326 intel 27218
Contextual Info: Ä E W Ä K l ! D M F fö ß iflÄ irD © rc ] in te l SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

intel PLD

Contextual Info: INTEL CORP UP/PRPHLS . • i n t g MME D ■ - . MÔSbl75 0101313 5 I ■ ITLl ' p ftg y o m M ? l " P i - 6 - 1^ - 27960CX PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM Pipelined Addressing fo r Optimal Bus Bandwidth on 80960CA — N ext Addressing Overlaps Last Data

1N4002

Abstract: 80960CF 80960Cx
Contextual Info: Designing for 80960Cx and 80960Hx Compatibility Application Note December 1997 Order Number: 272556-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

8510H

Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA AP-716 MCON00
Contextual Info: A AP-716 APPLICATION NOTE 80960Cx/80960Jx/80960Hx Architectural Comparison Tom Johnson SPG 80960 Systems Engineer Intel Corporation Mail Stop CH6-311 5000 W. Chandler Blvd. Chandler, Arizona 85226 January 29, 1996 Order Number: 272694-001 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability

D8905

Abstract: "printer controller"
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D8905 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 40960Sx, 80960Kx, 80960Cx Programmable Wait States For Various Memory and I/O Devices Supports Interleave Memory

VA80960CA25

Abstract: VA80960CA-16 80960CA va80960 VA80960CA16 de sw033 i960 Cx Instruction Set Quick Reference Multi-Channel DMA Controller 80960CF A20A
Contextual Info: 80960CA/CF SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272875-001 The 80960CA/CF may contain design defects or errors known as errata. Characterized errata that may cause the 80960CA/CF’s behavior to deviate from published specifications are documented

16V8H-15

Abstract: 20-2136J res 10k sip 16V8H-15 pc IC 4020 pulse TRANSFORMER valor res 0402 MSL-260-G-H ic 0808 data sheet 16v8h
Contextual Info: PLX Technology PCI9060 DEMO List of Materials 06/16/96 Description Qty Vendor Vendor Part Reference Designator PCB,PCI9060 DEMO,Rev A IC,PCI9060,PQFP IC,80960CA,33 MHz,PQFP IC,82596CA,33 MHz,PFQP IC,82C503,PLCC IC,16550A,PLCC IC,Static Ram, 32Kx8, 15 nsec, 28 Pin 300 Mil SOJ

Contextual Info: Ä I D W M C S Ö M F @ [^ M Ä ?D [K 1 ir tU October 1989 3 80960CA Product Overview 32-Bit High-Performance Embedded Processor with On-Chip DMA Controller, Interrupt Controller, High-Speed Bus Unit, Instruction and Register Caches Order Number: 270669-001

TA80960KB25

Abstract: TA80960KB TA80960KB16 A80960CA33 A80960CA25 A8095925 300v 80959CF A80960MC25 intel i960
Contextual Info: Intel i960 processors by Part Number and Description Level 1 Product Material Material Long Description A80959CF40 802751 32BIT MPU 80959CF 40 40 4KBCPGA168 COMM 1KB 5.000V TRAY EBOND OUT 80960CF25 803021 32BIT MPU 80960CF 25 25 4KBCPGA168 COMM 1KB 5.000V TRAY E

Contextual Info: w 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: iny SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 M bytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture

DT 94

Abstract: 80960CA
Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060 FLASH EPROM WRITE 80960CA , 1 WORD [PWR_960.TD] (07/12/94) STATE A 3 2 1 D A PCLK1-33 [3,14] [3,14] LA[2.31], LBE[0.3] [3,16] [3,16] LD[0.7] [6,18] [6,18] [6,18] [6,18] [3,18] [3,18] ADS~ LW/R [5,16] [5,16] BLAST~

S337

Abstract: Diode S4 DT 94 80960CA
Contextual Info: 0ns TITLE 100ns 200ns 300ns 400ns PCI9060 UART READ 80960CA , 1 WORD [URD_960.TD] (07/12/94) STATE 6 7 A 5 4 3 2 1 D A <2.92,> <-0.5,> PCLK1-33 [3,14] [3,14] LA[2.31], LBE[0.3] [6,18] [6,18] ADS~ [3,18] [3,18] LW/R [5,16] [5,16] BLAST~ [3,14] [3,14] DT/R

va80960ca25

Abstract: va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
Contextual Info: 80960Cx Processor Specification Update October 1998 Notice: The 80960Cx processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.

T3I marking code

Abstract: 27960CX 80960CA 85C508 N27960CX Marking code varc 29023
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

27960CX

Abstract: 80960CA 85C508 N27960CX 3A353
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

29023

Contextual Info: ln¥ I A E W M 1 ! DMIF@®IM]ATrO@M 27960CX PIPELINED BURST ACCESS 1M 128K x 8 EPROM Synchronous 4 Byte Data Burst Access Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte No Glue Interface to 80960CA