32BIT Search Results

45VM32160D

Contextual Info: IS42/45VM32160D 4M x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42/45VM32160D are mobile 536,870,912 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are

K4S643233H

Abstract: K4S643233H-F
Contextual Info: K4S643233H - F H E/N/G/C/L/F Mobile-SDRAM 512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4S643233H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,

K4S28323LF

Abstract: K4S28323LF-F
Contextual Info: K4S28323LF - F H E/N/S/C/L/R Mobile-SDRAM 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 2.5V power supply. The K4S28323LF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,

GDDR

Abstract: K4D553238E-JC33 k4d553238e-jc40
Contextual Info: 256M GDDR SDRAM K4D553238E-JC 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.3 August 2003 Samsung Electronics reserves the right to change products or specification without notice.

ba1s

Contextual Info: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data

Contextual Info: 32bit TX System RISC TX19 family TMP1942FDU/XBG Rev1.0 March 29, 2007 TMP1942FD 32-Bit RISC Microprocessor TX19 Family TMP1942FDU/FDXBG 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture.

TPS65381-Q1

Abstract: pin configuration of transistor d313 TPS65381 tms570 Interrupt m117 code d114 digital transistor airbag inductor
Contextual Info: TPS65381-Q1 www.ti.com SLVSBC4 – MAY 2012 Multi-Rail Power Supply for Microcontrollers in Safety-Critical Applications FEATURES 1 • 2 • • 1 2 Multi-Rail Power Supply Supporting Among Others: – Texas Instruments TMS570LS Series 16/32Bit RISC Flash Microcontroller

SM32200K

Abstract: IS42SM32200K
Contextual Info: IS42SM/RM/VM32200K 512K x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42SM/RM/VM32200K are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are

Contextual Info: THCV218_Rev.1.00_E_Brief THCV218 V-by-One HS High-speed video data receiver General Description Features THCV218 is designed to support video data transmission between the host and display. One high-speed lane can carry up to 32bit data and 3 bits of synchronizing signals at a pixel clock

NT5DS4M32EF-25

Abstract: NT5DS4M32EF-28 NT5DS4M32EF-33 NT5DS4M32EF-4
Contextual Info: NT5DS4M32EF 4Mx32 Double Data Rate SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM With Bi-directional Data Strobe and DLL 144-Ball FBGA Nanya Technology Corp. NTC reserves the right to change products or specification without notice.

K4M283233H

Contextual Info: K4M283233H - F H N/G/L/F Mobile SDRAM 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4M283233H is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,

LPC-H2129

Abstract: olimex LPC2129 ARM7TDMI-S programming LPC2129 ARM7TDMI-S lpc2129 pin arm lpc2129 programmer schematic arm pic 16 Programming Bootloader LPC2129 board MSP430
Contextual Info: LPC-H2129 HEADER BOARD FOR LPC2129 ARM7TDMI-S MICROCONTROLLER Features: • MCU: LPC2129 16/32 bit ARM7TDMI-S with 256K Bytes Program Flash, 16K Bytes RAM, RTC, 4x 10 bit ADC 2.44 uS, 2x UART, 2x CAN, I2C, SPI, 2x 32bit TIMERS, 7x CCR, 6x PWM, WDT, 5V tolerant I/O, up to 60MHz operation

CS494001-CQ

Abstract: Pacific Microsonics IEC-61937 CS49400-CQ UHS-1 hdcd CS49300 CS494501-CQ 33k ohm resistor IEC61937 MLP
Contextual Info: CS49400 Audio Decoder & Programmable 32-bit DSP Family - Product Brief Features Multi-standard Audio Decoder The CS49400 DSP family integrates a programmable multi-channel audio decoder and a high performance 32bit audio processor with an audio optimized software

Contextual Info: Section 1 H8S/2245 Series Features 1.1 H8S/2245 Series Functions H8S/2245 Series microcomputers are designed for faster instruction execution, using a realtime control oriented CPU with an internal 32bit architecture, and can run programs based on the C high-level language efficiently. As well as large-capacity ROM and RAM, these microcomputers

46LR32640A

Abstract: Mobile DDR SDRAM
Contextual Info: IS43/46LR32640A 16M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

4 Banks x 1m x 32Bit Synchronous DRAM

Contextual Info: HY57V283220 L T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision No. History 0.1 Defined Preliminary Specification 0.2 1) 2) 3) 4) 5) 6) 0.3 Defined IDD Spec. 0.4 Delited Preliminary. 0.5 Changed IDD Spec. 0.6 133MHz Speed Added

Contextual Info: N32D3225LPAW 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These N32D3225LPAW are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are

Contextual Info: N128D3218LPAF2 Advance Information 1M x 32Bits x 4Banks Mobile Synchronous DRAM Description These N128D3218LPAF2 are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are

Contextual Info: IS42RM32400F Advanced Information 1M x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42RM32400F are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are

Contextual Info: K4S643234E-SE/N CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL 2.5V Extended Temperature 90-Ball FBGA Revision 1.8 April 2002 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.8 April 2002

A45L9332A

Contextual Info: A45L9332A Series Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History History Issue Date Remark 0.0 Initial issue August 21, 2001 Preliminary 0.1 Update AC and DC data specification

Q 2 72 t5

Abstract: Q 72 t5 T436432B T436432B-55SG T436432B-5S T436432B-5SG
Contextual Info: tm TE CH T436432B SDRAM 512K x 32bit x 4Banks Synchronous DRAM FEATURES GRNERAL DESCRIPTION 2M x 32 SDRAM • • • • • 3.3V power supply Clock cycle time : 5 / 5.5 / 6 / 7 / 8 / 10 ns Internal four banks operation LVTTL compatible with multiplexed address

intel CORE i3 instruction set

Abstract: intel packaging handbook 240800
Contextual Info: 80960JA/JF/JD/JT 3.3 V Embedded 32Bit Microprocessor Preliminary Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JA/JF lx the Bus Clock

Contextual Info: HY5W2A2 L/S F / HY57W2A3220(L/S)T HY5W22F / HY57W283220T 4Banks x 1M x 32bits Synchronous DRAM Revision History Revision No. History 0.3 Changed TA, PKG Drawing, Output Load Circuit 0.4 Changed Cin Value. 0.6 1. Added Operation Code in Mode Register 2. Changed Burst Stop in Full Page