GDDR Search Results

2N2007E

Abstract: 2N2007 CAP 10nF 50V 0603 18126D107MAT 597D108X06
Contextual Info: MIC5162 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination General Description Features The MIC5162 is a dual regulator controller designed for highspeed bus termination. It offers a simple, low-cost JEDEC compliant solution for terminating high-speed, lowvoltage digital buses i.e. DDR, DD2, DDR3, SCSI, GTL,

GDDR

Abstract: K4D553238E-JC33 k4d553238e-jc40
Contextual Info: 256M GDDR SDRAM K4D553238E-JC 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.3 August 2003 Samsung Electronics reserves the right to change products or specification without notice.

k4n26323ae

Abstract: K4N26 K4N26323AE-GC20 K4N26323AE-GC22 K4N26323AE-GC25
Contextual Info: 128M GDDR2 SDRAM K4N26323AE-GC 128Mbit GDDR2 SDRAM 1M x 32Bit x 4 Banks GDDR2 SDRAM with Differential Data Strobe and DLL Revision 1.7 January 2003 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.7 Jan. 2003

hyb18h1g321af-11

Abstract: qimonda hyb18h
Contextual Info: June 2007 HYB18H 1G 321 A F- 1 1 / 1 4 GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM RoHS compliant Data S heet Rev. 0.80 Data Sheet HYB18H1G321AF-11/14 1-Gbit GDDR3 HYB18H1G321AF-11/14 Preliminary Revision History: 2007-06, Rev. 0.80 Page Subjects major changes since last revision

HYB18H512321B2F-14

Contextual Info: March 2008 HYB18H512321B2F–12/14 GDDR3 Graphics RAM 512-Mbit GDDR3 Graphics RAM RoHS compliant Advance Internet Data Sheet Rev. 0.70 Advance Internet Data Sheet HYB18H512321B2F 512-Mbit GDDR3 HYB18H512321B2F–12/14 Revision History: 2008-03, Rev. 0.70 Page

W641GG2KB

Abstract: gddr3 schematic WBGA-136 W641GG2
Contextual Info: W641GG2KB 1-Gbit GDDR3 Graphics SDRAM Table of Contents 1. GENERAL DESCRIPTION . 6 2. FEATURES . 7

DDR3 pcb layout guidelines

Abstract: MIC5162YMM DDR3 pcb layout CRCW06031K00FKTA C1608X5R0J106M C2012X5R0J226M GRM188R60J106ME47D GRM21BR60J226ME39L MIC5162 MSOP-10
Contextual Info: MIC5162 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination General Description Features The MIC5162 is a dual regulator controller designed for • Input voltage range: 1.35V to 6V high speed bus termination. It offers a simple, low-cost

qimonda hyb18h5

Abstract: HYB18H512321BF HYB18H512321BF-10 HYB18H512321BF-08/10 gddr3 HYB18H512
Contextual Info: September 2007 HYB18H512321BF–11/12/14 HYB18H512321BF–08/10 512-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM RoHS compliant Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 HYB18H512321BF–11/12/14 HYB18H512321BF–08/10 Revision History: 2007-09, Rev. 1.1

HYB18H1G321AF-10/11/14

Abstract: HYB18H1G321AF CL11 SEN 1327 hyb18h1g321af-11 Qimonda AG HYB18H1G321AF A 1837 3G3M
Contextual Info: October 2007 HYB18H1G321AF–10/11/14 GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM RoHS compliant Internet Data Sheet Rev. 0.92 Internet Data Sheet HYB18H1G321AF–10/11/14 1-Gbit GDDR3 HYB18H1G321AF–10/11/14 Revision History: 2007-10, Rev. 0.92 Page Subjects major changes since last revision

HY5DS283222BF

Abstract: HY5DS283222BFP-33
Contextual Info: HY5DS283222BF P 128M(4Mx32) GDDR SDRAM HY5DS283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

POWER COMMAND HM 1211

Abstract: power generation POWER COMMAND HM 1211 6331-1 gddr3 schematic HYB18T256324F-20 infineon sgram
Contextual Info: Data Sheet, Rev. 1.11, April 2005 HYB18T256324F–16 HYB18T256324F–20 HYB18T256324F–22 256-Mbit GDDR3 DRAM [600MHz] RoHS compliant Memory Products N e v e r s t o p t h i n k i n g . Edition 04-2005 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

E4690

Contextual Info: cPCI-R6700 Series 6U CompactPCI Rear Transition Module with ATI/AMD Radeon E4690 GPU 1 AdvancedTCA Features ATI/AMD Radeon™ E4690 embedded GPU 512MB on-chip GDDR3 VRAM Supports dual independent DVI-I displays Onboard VBIOS update available PICMG 2.16 Packet Switch Backplane R1.0

BT 4840 amp

Abstract: K4D261638K-LC50 K4D261638K-LC40 cs 2648 k4d261638k 3620* IBIS
Contextual Info: K4D261638K 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.2 November 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

Contextual Info: 128M GDDR SDRAM K4D263238I-VC 128Mbit GDDR SDRAM Revision 1.2 January 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: 256M GDDR3 SDRAM K4J55323QG 256Mbit GDDR3 SDRAM Revision 1.2 March 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

timing controller SHART

Abstract: T21N K4U52324Q SAMSUNG GDDR4 K4U52324QE-BC09 GDDR4
Contextual Info: 512M GDDR4 SGRAM K4U52324QE 512Mbit GDDR4 SGRAM 2M x 32Bit x 8 Banks Graphic Double Data Rate 4 Synchronous DRAM with Uni-directional Data Strobe and DLL 136Ball FBGA Revision 1.0 June 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

Contextual Info: Primarily 128M GDDR SDRAM K4D263238I-VC 128Mbit GDDR SDRAM Revision 0.1 Sep 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: 128M GDDR SDRAM K4D263238I-UC 128Mbit GDDR SDRAM Revision 1.1 January 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

K4D263238G-VC33

Contextual Info: 128M GDDR SDRAM K4D263238G-GC 128Mbit GDDR SDRAM 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.7 February 2005 Samsung Electronics reserves the right to change products or specification without notice.

K4J10324KE-HC1A

Abstract: K4J10324KE-HC14 T21N K4J10324KE k4j10324 K4J10324KE-HC12
Contextual Info: Target 1Gb GDDR3 SDRAM K4J10324KE 1Gbit GDDR3 SDRAM 136FBGA with Halogen-Free & Lead-Free RoHS compliant Revision 0.1 December 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

GDDR

Abstract: K4D551638H-LC50
Contextual Info: K4D551638H 256M GDDR SDRAM 256Mbit GDDR SDRAM Revision 1.3 April 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

tsop-ii 66 JEDEC TRAY

Contextual Info: 128M GDDR SDRAM K4D261638F 128Mbit GDDR SDRAM Revision 1.5 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

K4D263238I-VC50

Contextual Info: Target 128M GDDR SDRAM K4D263238I-VC 128Mbit GDDR SDRAM Revision 0.0 May 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: 128M GDDR SDRAM K4D261638F 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.5 March 2005 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.5 Mar. 2005 128M GDDR SDRAM