CS9060 Search Results

LD31

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300ns POWERPC , 1 WORD READ FROM PCI9060 INTERNAL REGISTERS [PPCRD1.TD] 01/24/96 STATE LCLK-25 [4,15] [4,15] A[6:29] [3,11] [3,11] [3,12] [3,12] [2,12] [2,12] PR/W WBE[0:3] CS1~ [3,10] [3,10 CS9060~ [0,0] [0,0] LA[25:2]

OSCILLATOR

Abstract: transistor oscillator circuit MACH210 addr 403GC PCI9060ES 252a LD31
Contextual Info: ADDR MUX MACH210 DRAM PCI9060ES 403GC CPU LD[31:0] D[31:0] LA[25:2] A[6:29] LA[31:26] LHOLD HOLDACK ADS~ CS1~ LW/R PR/W BLAST~ READY LBE[3:0] WBE[3:0] RDYO ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1] WAITI~ OSCILLATOR DIV/2 HOLDREQ LHOLD A PCI BUS 50 MHz MACH210

plx9060

Abstract: U0201 LD11 93cs46 LD12 LD17 LD18 LD19 ld-16
Contextual Info: 1 2 3 4 5 6 7 8 VCC LD[0.15] LA[2.10] B C LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126 127 128 129 130 131 132 133 135 136 LA[2.10] 19 18 17 3 CS9060~ 3 147 146 169 150 159 151

TCI diode

Abstract: U0401 TIP 41 transistor LA29 LA30 16v8c
Contextual Info: 1 LA[2.31] 2 3 4 5 6 7 8 LA[2.31] LA28 LA29 LA30 LA31 U0401 BCLK3 BCLK3 A TS~ TIP~ R/W TT0 TT1 TS~ TIP~ R/W TT0 TT1 BR~ BB~ LOCK040~ BR~ BB~ LOCK040~ READYO~ SRRDY~ LHOLD BREQO READYO~ SRRDY~ LHOLD BREQO ADS~ TT0 CS9060~ TS~ BB~ R/W TT1 LOCK040~ SRRDY~ TIP~

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

MACH210A

Contextual Info: module busctl title ' PLX TECHNOLOGY * PROPRIETARY INFORMATION * BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI 9060/68040 Demo Board Part Number: xxx-xxxx-xxxx Revision 1.0 07-18-95 Copyright PLX Technology, 1995 ' "device declaration

93CS46

Abstract: 0x00000018 E 32.0000 C 10B5 c code for pci master
Contextual Info: PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • • • • • • • • PCI9060 bridge between Primary PCI Bus and Intel

la1 d22

Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH

PD0404

Abstract: U0401 U0403 pu0403 DIP10 16V8R LA29 LA30 I11I12
Contextual Info: 1 2 3 4 5 6 7 8 PCLK1B LA[2.31] A LA[2.31] LA3 LA28 LA29 LA30 LA31 RESET~ ADS~ BLAST~ WAIT~ READYO~ IORDY~ RESET~ ADS~ BLAST~ WAIT~ READYO~ PU0401 PD0401 1 2 3 4 5 6 7 8 9 10 11 14 23 13 U0401 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4

Y0803

Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Contextual Info: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5

H 04 D 35

Abstract: h9 ck 403GC 9060ES LA25 MACH210A PCI9060ES
Contextual Info: "* "*Proprietary Rights Notice: * "* * "*This material contains the valuable proprietary and trade * "*secret information of PLX Technology of Mountain View, * "*California. No part of such information

L1144

Abstract: l0728 l0312 L0936 l0832 L1248 l2904 L4516 L7940 L0624
Contextual Info: ˆABEL 5.02 Data I/O Corp. JEDEC file for: MACH220A V1.3 Created on: Tue Oct 24 14:16:42 1995 PLX TECHNOLOGY PROPRIETARY INFORMATION BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI MPEG Board Part Number: xxx-xxxx-xxxx Revision 3.0 10-20-95 Copyright PLX Technology, 1995

L1239

Abstract: l0728 l0312 SGS L282 L0936 L11616 L9960 0x00000404 L1198 L1322
Contextual Info: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _

ld18

Abstract: LD11 ld12 LD17 LD19 LD20 LD31 LA15 LA18 LD26
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.31] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126

403GA

Abstract: PCI9060ES PLX Technology 403GC 9060ES MACH210 powerpc 403 16v8s
Contextual Info: PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a PCIbus interface PCI 9060ES chip supports master, slave and PCI

16V8-10

Abstract: U0801A
Contextual Info: PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a PCIbus interface PCI 9060ES chip supports master, slave and PCI

68040* part numbering

Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Contextual Info: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _

Contextual Info: "* "*Proprietary Rights Notice: * "* * "*This material contains the valuable proprietary and trade * "*secret information of PLX of Mountain View, California. * "*No part of such information *

u0304

Abstract: 16V8-10 LA29 LA30 LA25 16v810 R0302 PD0301
Contextual Info: LA[2.31] LA[2.31] U0301 LA24 LA25 LA26 LA27 LBE0~ LBE1~ LBE2~ LBE3~ A7 (A6) (A5) (A4) LBE0~ LBE1~ LBE2~ LBE3~ LHOLD HOLDACK CS1~ XACK~ LHOLD HOLDACK CS1~ XACK~ LCLKB LRESET~ ADS~ LW/R BLAST~ RDYO~ LCLKB LRESET~ ADS~ LW/R BLAST~ RDYO~ ADS~ BLAST~ READY

ld18

Abstract: ld25 LA29 LA18 LD11 LD12 LD17 LD19 LD20 PU0207
Contextual Info: VCC LD[0.31] LA[2.31] LD[0.31] 1 2223390 4590190 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 5 4 3 2 207 206 205 204 203 202 201 200 199 198 197 196

16V8-10

Abstract: semiconductor ad 5.9 u0304 R0801 74ACT74 LD11 LD12 U0801A LA17 MXA0 A10
Contextual Info: ECN HISTORY |LINK |N2.SCH |N3.SCH |N4.SCH |N5.SCH |N6.SCH |N7.SCH SPARE GATES: DESCRIPTION DATE REV 1 - 01/24/96 REV 2 -CHANGED DRMMUX 2/17/96 APPROVAL PU0101 1 PU0102 PU0103 12 11 D P R U0303B Q 9 CLK C L 1 3 Q 8 74ACT74 PU0104 APPROVALS DATE PLX TECHNOLOGY

ld18

Abstract: LD11 R0201 93cs06 LA18 LD17 LD19 LD20 LD12 U0201
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.31] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126

L0936

Abstract: l0728 L1239 L0988 L9960 l0312 l0832 L4204 l0416 L9804
Contextual Info: module busctl title ’ PLX TECHNOLOGY * PROPRIETARY INFORMATION * BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI MPEG Board Part Number: xxx-xxxx-xxxx Revision 3.0 10-20-95 Copyright PLX Technology, 1995 ’ "device declaration

STI3400

Abstract: STI4500
Contextual Info: module busctl title ’ PLX TECHNOLOGY * PROPRIETARY INFORMATION * BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI MPEG Board Part Number: xxx-xxxx-xxxx Revision 3.0 10-20-95 Copyright PLX Technology, 1995 ’ "device declaration