RN0804
Abstract: PD0302 68040 93CS06 RN0801 PD0501 c14 c13 PD0201 PU0201 PU0203
Contextual Info: 1 2 ADS~ LW/R BLAST~ READYO~ TS~ TIP~ BB~ LOCK040~ PU0201 A 1 2 3 4 5 6 7 8 9 10 VCC 3 RN0801 COM IN IN IN IN IN IN IN IN IN PU0202 PU0203 PU0301 PU0302 PU0303 PU0304 PU0305 PU0306 PU0307 1 2 3 4 5 6 7 8 9 10 VCC 4 RN0802 COM IN IN IN IN IN IN IN IN IN PU0601
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LOCK040~
PU0201
RN0801
PU0202
PU0203
PU0301
PU0302
PU0303
PU0304
PU0305
RN0804
PD0302
68040
93CS06
RN0801
PD0501
c14 c13
PD0201
PU0201
PU0203
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ACT04
Abstract: ACT14 INT9060 RN1101
Contextual Info: 1 A ADS~ LW/R BLAST~ READYO~ DEN~ DT/R WAIT~ LOCK~ INT9060~ 2 1 2 3 4 5 6 7 8 9 10 VCC RN1101 COM IN IN IN IN IN IN IN IN IN PU0202 PU0201 PU0204 PU0205 PU0203 PU0206 PU0208 PU0207 PU0209 3 1 2 3 4 5 6 7 8 9 10 VCC PU4.7K PU0604 PU0701 PU0702 PU0703 PU0704
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INT9060~
RN1101
PU0202
PU0201
PU0204
PU0205
PU0203
PU0206
PU0208
PU0207
ACT04
ACT14
INT9060
RN1101
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lm7805
Abstract: lm7805 datasheet header 20X2 LD11
Contextual Info: 1 2 3 +5V +5V 1 2 3 4 5 6 7 8 9 10 PU0101 PU0102 PU0103 PU0104 A 4 2LINTO~ 2 ADS~ 2BLAST~ 2 LW/R 1 2 3 4 5 6 7 8 9 10 PU0201 PU0401 PU0402 PU0403 PU0404 PU0501 PU0502 PU0601 PU0602 CLK25A 2 2 LA1 LA[2.10] RN0902 COM IN IN IN IN IN IN IN IN IN RN0903 1 2 3
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PU0101
PU0102
PU0103
PU0104
PU0201
PU0401
PU0402
PU0403
PU0404
PU0501
lm7805
lm7805 datasheet
header 20X2
LD11
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c14 c13
Abstract: PD0206
Contextual Info: 1 2 ADS~ LW/R BLAST~ PU0201 PU0202 PU0203 PU0301 PU0401 PU0501 A 1 2 3 4 5 6 7 8 9 10 VCC 3 RN0701 COM IN IN IN IN IN IN IN IN IN 4 1 2 3 4 5 6 7 8 9 10 PD0201 PD0202 PD0203 PD0204 PD0205 PD0206 PD0207 5 RN0702 COM IN IN IN IN IN IN IN IN IN 8 COM IN IN IN
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PU0201
PU0202
PU0203
PU0301
PU0401
PU0501
RN0701
PD0201
PD0202
PD0203
c14 c13
PD0206
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MSL260G
Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
MSL260G
MSL-260-G
D0806
R0807
T0803
D0802
D0807
RDD0804
D0808
5 pin reset ic ARB
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PDF
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LD18
Abstract: LA18 LD30 LD11 U0201 AD20-AD21 la16 LD22 LD25 LD17
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.22] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126 127 128 129 130 131 132 133 135 136 C 19 18
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PD0201
PU0201
PU0202
PD0202
PD0203
PD0204
PD0205
PD0206
PCI9060,
PCI9060/DRAM
LD18
LA18
LD30
LD11
U0201
AD20-AD21
la16
LD22
LD25
LD17
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la1 d22
Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH
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U0101
PCI9060,
80960CA
U0102
20V8R
PCI9060
PCI9060/68040
la1 d22
la2 d2 timer
rn0805
U0301
L16 eeprom
LD11
LD12
U0101
PCI9060 68040
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Y0803
Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Contextual Info: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5
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U0101
PU0101
PU0102
PU0103
U0801B
74ACT74
20V8C
PU0104
Y0803
U0801B
IC LM7805
N1 Y10
pin diagram of IC LM7805
C0801
STI3400
U0101
U0604
plx9060
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mah8
Abstract: MDL22 u0502a LD11 LD12 U0101 RN05 RN0501 U0302
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH 7
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U0101
PCI9060,
9060/DRAM
U0102
20V8R
PCI9060
PCI9060/DRAM
mah8
MDL22
u0502a
LD11
LD12
U0101
RN05
RN0501
U0302
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L1239
Abstract: l0728 l0312 SGS L282 L0936 L11616 L9960 0x00000404 L1198 L1322
Contextual Info: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _
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9060/MPEG
L1239
l0728
l0312
SGS L282
L0936
L11616
L9960
0x00000404
L1198
L1322
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ld18
Abstract: LD11 ld12 LD17 LD19 LD20 LD31 LA15 LA18 LD26
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.31] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126
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CS9060~
PD0201
PU0201
PU0202
PD0202
PD0203
PD0204
PD0205
PD0206
PCI9060,
ld18
LD11
ld12
LD17
LD19
LD20
LD31
LA15
LA18
LD26
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D0807
Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Contextual Info: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors
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PCI9060
PCI9060,
80960CA
82596CA
U0101
20V8R
U0102
PCI9060
D0807
C0702
D0801
D0806
R0807
T0803
D0808
D0802
RDD0804
C0705
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68040* part numbering
Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Contextual Info: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _
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PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
68040* part numbering
93CS46
SR96
L16 eeprom
Motorola 68040
Pal programming
10B5
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ld18
Abstract: LD11 R0201 93cs06 LA18 LD17 LD19 LD20 LD12 U0201
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.31] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126
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CS9060~
PU0201
PU0202
BREQ9060
HLDA9060
INT596~
PCI9060,
PCI9060
ld18
LD11
R0201
93cs06
LA18
LD17
LD19
LD20
LD12
U0201
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1N4148/2 pin connector sip
Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Contextual Info: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
1N4148/2 pin connector sip
ACT04 MOTOROLA
1N4148 D0805
pal programming
sw dip-3
80960CA
15 pin through hole d sub connector
16v8h
DIODE MOTOROLA B33
D0805
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PDF
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plx9060
Abstract: U0201 LD11 93cs46 LD12 LD17 LD18 LD19 ld-16
Contextual Info: 1 2 3 4 5 6 7 8 VCC LD[0.15] LA[2.10] B C LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126 127 128 129 130 131 132 133 135 136 LA[2.10] 19 18 17 3 CS9060~ 3 147 146 169 150 159 151
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CS9060~
PD0201
CLK25A
PD0202
PD0203
PD0204
PD0205
PD0206
SERR11
PLX9060
U0201
LD11
93cs46
LD12
LD17
LD18
LD19
ld-16
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L0936
Abstract: L0988 L9960 L1239 STI3400 L1462 E442 L1105 L3216 U0601
Contextual Info: Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _ General Description _ Features_
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9060/MPEG
L0936
L0988
L9960
L1239
STI3400
L1462
E442
L1105
L3216
U0601
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PDF
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10B5
Abstract: 93CS46
Contextual Info: Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • •
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PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
10B5
93CS46
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code h7f
Abstract: datasheet LD9 m mah8 MDL22 MDL14 fuse 9060ES A3-12 LD11 MACH210A U0101
Contextual Info: Go to next Section: PowerPC 403 to PCI 9060ES Return to Table of Contents Designing a PCI Memory Board No CPU, DRAM Control examples PLX PCI9060 DRAM Controller Application Note Revision 1.0 September 8, 1995 PLX Technology, Inc. 625 Clyde Avenue, Mt View, California 94043
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9060ES
PCI9060
9060/DRAM
100ns
150ns
PCI9060
BCLK-33
code h7f
datasheet LD9 m
mah8
MDL22
MDL14 fuse
9060ES
A3-12
LD11
MACH210A
U0101
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D0802
Abstract: D0807 C0702 16v8c T0803 D0806 R0807 D0808 RDD0804 pt3868
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 20V8R DIP 9 U0102 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11
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U0101
20V8R
U0102
PCI9060,
80960CA
82596CA
PCI9060
PCI9060
D0802
D0807
C0702
16v8c
T0803
D0806
R0807
D0808
RDD0804
pt3868
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