80960CA Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: Wfwl LETT mLrJk HEW PACKARD H P E2432A Intel 80960CA/CF Preprocessor Interface For use with HP logic analyzers The HP E2432A preprocessor interface for the Intel 80960CA/CF is a mechani­ cal and electrical interface between the Intel 80960CA/CF and various HP logic analyzers

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

Non-Pipelined processor

Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining

270710

Abstract: CX041A
Contextual Info: ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

xxnx

Abstract: 1bw 85 271326 intel 27218
Contextual Info: Ä E W Ä K l ! D M F fö ß iflÄ irD © rc ] in te l SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

intel PLD

Contextual Info: INTEL CORP UP/PRPHLS . • i n t g MME D ■ - . MÔSbl75 0101313 5 I ■ ITLl ' p ftg y o m M ? l " P i - 6 - 1^ - 27960CX PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM Pipelined Addressing fo r Optimal Bus Bandwidth on 80960CA — N ext Addressing Overlaps Last Data

VA80960CA25

Abstract: VA80960CA-16 80960CA va80960 VA80960CA16 de sw033 i960 Cx Instruction Set Quick Reference Multi-Channel DMA Controller 80960CF A20A
Contextual Info: 80960CA/CF SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272875-001 The 80960CA/CF may contain design defects or errors known as errata. Characterized errata that may cause the 80960CA/CF’s behavior to deviate from published specifications are documented

16V8H-15

Abstract: 20-2136J res 10k sip 16V8H-15 pc IC 4020 pulse TRANSFORMER valor res 0402 MSL-260-G-H ic 0808 data sheet 16v8h
Contextual Info: PLX Technology PCI9060 DEMO List of Materials 06/16/96 Description Qty Vendor Vendor Part Reference Designator PCB,PCI9060 DEMO,Rev A IC,PCI9060,PQFP IC,80960CA,33 MHz,PQFP IC,82596CA,33 MHz,PFQP IC,82C503,PLCC IC,16550A,PLCC IC,Static Ram, 32Kx8, 15 nsec, 28 Pin 300 Mil SOJ

D0807

Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Contextual Info: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors

Contextual Info: Ä I D W M C S Ö M F @ [^ M Ä ?D [K 1 ir tU October 1989 3 80960CA Product Overview 32-Bit High-Performance Embedded Processor with On-Chip DMA Controller, Interrupt Controller, High-Speed Bus Unit, Instruction and Register Caches Order Number: 270669-001

Contextual Info: w 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: iny SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 M bytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture

S337

Abstract: Diode S4 DT 94 80960CA
Contextual Info: 0ns TITLE 100ns 200ns 300ns 400ns PCI9060 UART READ 80960CA , 1 WORD [URD_960.TD] (07/12/94) STATE 6 7 A 5 4 3 2 1 D A <2.92,> <-0.5,> PCLK1-33 [3,14] [3,14] LA[2.31], LBE[0.3] [6,18] [6,18] ADS~ [3,18] [3,18] LW/R [5,16] [5,16] BLAST~ [3,14] [3,14] DT/R

T3I marking code

Abstract: 27960CX 80960CA 85C508 N27960CX Marking code varc 29023
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

27960CX

Abstract: 80960CA 85C508 N27960CX 3A353
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

29023

Contextual Info: ln¥ I A E W M 1 ! DMIF@®IM]ATrO@M 27960CX PIPELINED BURST ACCESS 1M 128K x 8 EPROM Synchronous 4 Byte Data Burst Access Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte No Glue Interface to 80960CA

cl-001

Abstract: 85C508 Intel 85C508 80960CA 27960CX intel PLD
Contextual Info: IP ^ iy M O G M V intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte CHMOS Ill-E for High Performance and Low Power — 125 mA Active, 30 mA Standby

Non-Pipelined processor

Abstract: 80960CF 80960CA 80960CF-33 80960CF-40 D1447
Contextual Info: CFMAST01.BK Page i Thursday, April 25, 2002 9:08 AM A 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution

Contextual Info: Ä P m K K g l 0 MF [F3[ifflAT0®[N] SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

Contextual Info: in te l SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining i • 32-bit Parallel Architecture

Contextual Info: in te l 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining

NRED 61

Abstract: HT21X
Contextual Info: in tj 80960CA-33, -25, -16 32-BIT HIGH PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution