CK 77 Search Results

NT5DS32M4AT-7K

Abstract: DDR200 DDR266A DDR266B NT5DS16M8AT NT5DS32M4AT PC2100 NT5DS16M8AT-7K
Contextual Info: NT5DS32M4AT NT5DS16M8AT 128Mb Double Data Rate SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions, also aligns QFC transitions with CK during Read cycles • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

socket FM2

Abstract: PZ90427-3126-01H
Contextual Info: o D E AS G EN E R A TE D D R A W IN G , D O N 'T CHANGE 3 BY 4 5 6 REV. HAND. 4 3 .0 8 ! _ A - a - j_ A SOCKE I D E T A IL A 77 FM2 A Cp£ LF a ^ D E T A IL APPD . BC-11-0034780 Di ck i e.H B BC-11-0107792 Di ck i e.H C BC-12-0010128 DI ck i e.H BC-12-0043322 Di ck i e.H

74374

Abstract: 74574 74534 ZD2020 74575
Contextual Info: - 246- 745 34 Octal 3-State D-FFs Inverted 7D c 7Q r f 5ff 6D 5D 55 S C p r r j l CK* - 1 — »CK OE ^ CK* — |p—4 *CK l £ J T ' I _CK* — <— *CK _ OUTPUT IQ CONTROL 10 , U 5 C P 2D '+ OE I r h _CK* — - * C K _ b 3 h I 4 CLOCK 25 3 i 30 40 i3 GN D

NT5DS32M16CS

Abstract: NT5DS32M16CS-5T NT5DS64M8CS-5T DDR333 DDR400 NT5DS64M8CG X32116 NT5DS64M8CS
Contextual Info: NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

DDR200

Abstract: DDR266 DDR333 W3EG6433S-AD4
Contextual Info: W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY* 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION „ DDR200, DDR266 and DDR333 „ Double-data-rate architecture „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#)

Contextual Info: White Electronic Designs W3EG7235S-JD3 PRELIMINARY* 256MB - 32Mx72 DDR SDRAM REGISTERED ECC, w/PLL FEATURES  Double-data-rate architecture  Speeds of 100MHz and 133MHz  Bi-directional data strobes DQS  Differential clock inputs (CK# & CK) 

Contextual Info: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY 1GB - 128Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#)

EM47FM0888MBA

Contextual Info: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation.

DDR200

Abstract: DDR266 DDR333 W3EG64128S-AD4
Contextual Info: W3EG64128S-AD4 -BD4 White Electronic Designs PRELIMINARY* 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL FEATURES DESCRIPTION „ Double-data-rate architecture „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#) „ Programmable Read Latency 2,2.5 (clock)

DDR200

Abstract: DDR266 DDR333 W3EG6464S-AD4
Contextual Info: W3EG6464S-AD4 -BD4 White Electronic Designs PRELIMINARY* 512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL FEATURES DESCRIPTION „ Double-data-rate architecture „ Speeds of 100MHz, 133MHz and 166MHz „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#)

schematic diagram of TV memory writer

Abstract: c28k OMRON Operation Manual C200H Pro27 OMRON Operation Manual OMRON PRO27 programming console C28H OMRON Operation Manual omron C60k cables pin diagram C20K-ETL01 Omron Programming Console PRO 27 omron c500 pro 13 C200H Pro27
Contextual Info: Issued March 1993 014-964 Data Pack D Data Sheet RS Omron CK range programmable logic controllers PLCs The Omron CK PLCs are a high specification, cost effective, compact range of programmable logic controllers (PLCs) which enable very flexible systems to

samsung 5230

Abstract: DDR200 DDR266 DDR333 W3EG72125S-D3
Contextual Info: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY* 1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#)

Contextual Info: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation.

Contextual Info: White Electronic Designs W3EG7232S-AD4 -BD4 PRELIMINARY* 256MB- 32Mx72 DDR SDRAM UNBUFFERED w/PLL FEATURES DESCRIPTION n Double-data-rate architecture n Clock speeds of 100MHz and 133MHz n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#)

znr k 270

Abstract: VARISTOR znr znr varistor ZNR 470 D 10 znr k 102 varistor znr k 680 znr k 150 varistor znr k 270 varistor ZNR 104 znr v 390
Contextual Info: “ZNR” Transient/Surge Absorbers Type CK UL and CSA Recognized “ZNR” Transient/Surge Absorbers with Tabs Type: CK ZNR Transient/Surge Absorber with Tabs is a heavy duty type ZNR with very unique tab terminals which bring forth a higher reliability.

znr k 270 varistor

Abstract: znr k 270 ZNR Transient Surge Absorbers
Contextual Info: “ZNR” Transient/Surge Absorbers Type CK UL and CSA Recognized “ZNR” Transient/Surge Absorbers with Tabs Type: CK ZNR Transient/Surge Absorber with Tabs is a heavy duty type ZNR with very unique tab terminals which bring forth a higher reliability.

varistor ck 260

Abstract: E321499
Contextual Info: “ZNR” Transient/Surge Absorbers Type CK UL and CSA Recognized “ZNR” Transient/Surge Absorbers with Tabs Type: CK ZNR Transient/Surge Absorber with Tabs is a heavy duty type ZNR with very unique tab terminals which bring forth a higher reliability.

Contextual Info: White Electronic Designs WED3EG6418S-D4 FINAL 128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL FEATURES n Double-data-rate architecture n Speed of 100MHz, 133MHz and 166MHz n Bi-directional data strobes DQS n Differential clock inputs (CK & CK#) n Programmable Read Latency 2,2,5 (clock)

VARISTOR znr

Abstract: varistor 05 k 575 varistor ck 32K241 varistor ck 260 32k201u 32k431 32K431U 40K201U znr k 820
Contextual Info: ÒZNRâÓ Transient/Surge Absorbers Type CK UL and CSA Recognized ÒZNRâÓ Transient/Surge Absorbers with Tabs Type: CK ZNR Transient/Surge Absorber with Tabs is a heavy duty type ZNR with very unique tab terminals which bring forth a higher reliability.

Contextual Info: ESM T M15F1G1664A DDR III SDRAM 8M x 16 Bit x 8 Banks DDR III SDRAM Features 1.5V ± 0.075V JEDEC Standard Power Supply 8 Internal memory banks (BA0- BA2) Differential clock input (CK, CK) Programmable CAS Output Driver Impedance Control Differential bidirectional data strobe

Contextual Info: ESM T M15F2G16128A DDR III SDRAM 16M x 16 Bit x 8 Banks DDR III SDRAM Feature 1.5V ± 0.075V JEDEC Standard Power Supply Output Driver Impedance Control 8 Internal memory banks (BA0- BA2) Differential bidirectional data strobe through ZQ pin Differential clock input (CK, CK )

TD62803P

Abstract: TD62803
Contextual Info: TD62803P TD62803P STEPPING MOTOR CONTROLLER/DRIVER Features • High-Voltage, High-Current Outputs V c e SUS <|>-28V(MIN), IQUT<i)=400niA (MAX) • 1,2, 1-2 Phase Excitation Mode Capable • 3 Inputs Direction Control . CK-1, CK-2 CW/CCW • Output Enable Function . E

Nanya nt5ds8m16fs

Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
Contextual Info: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

NT5DS32M8CS

Abstract: NT5DS16M16CS-5TI Nanya DDR333 DDR400 256mb ddr333 200 pin NT5DS16M16CS-5T
Contextual Info: NT5DS16M16CS NT5DS32M8CS NT5DS16M16CG 256Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2.5 DDR333 , 3(DDR400)