NT5DS128M4CG Search Results

NT5DS32M16CS

Abstract: NT5DS32M16CS-5T NT5DS64M8CS-5T DDR333 DDR400 NT5DS64M8CG X32116 NT5DS64M8CS
Contextual Info: NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

Contextual Info: NT5DS128M4CG 512Mb DDR SDRAM C-Die Preliminary Features • • • • • CAS Latency and Frequency CAS Latency 3 Maximum Operating Frequency MHz DDR400 (5T) 200 • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per

NT5DS32M16CS-5T

Abstract: NT5DS32M16CS Nanya Technology nt5ds32m16cs-6k NT5DS64M8CS-5T nt5ds64m8cg NT5DS32M16 NANYA DDR333 DDR400
Contextual Info: NT5DS32M16CS NT5DS64M8CS/NT5DS64M8CG NT5DS128M4CS 512Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

DDR400

Abstract: PC3200 NT5DS128M4CG-5T NT1GD72S4PC0FV-5T
Contextual Info: NT1GD72S4PC0FV/NT2GD72S4NCOFV 1GB: 128M x 72 / 2GB: 256M x 72 Low Profile Registered DDR SDRAM DIMM 184pin Low Profile Registered DDR SDRAM DIMM Based on 128Mx4 DDR SDRAM C Die device Features • 184 Dual In-Line Registered Memory Module RDIMM • Registered DDR DIMM based on 90nm 512Mb Die C device

Contextual Info: NT1GD72S4PC0FV/NT2GD72S4NCOFV 1GB: 128M x 72 / 2GB: 256M x 72 Low Profile Registered DDR SDRAM DIMM 184pin Low Profile Registered DDR SDRAM DIMM Based on 128Mx4 DDR SDRAM C Die device Features • 184 Dual In-Line Registered Memory Module RDIMM • Registered DDR DIMM based on 90nm 512Mb Die C device

NT5DS32M16CS-5T

Abstract: NT5DS64M8CS-5T NT5DS32M16CS nt5ds32m16cs-6k NT5DS64M8CG-5T NT5DS64M8CS-5TI NT5DS128M4CS-5T NT5DS128M4CS-6K DDR400 NT5DS64M8CG
Contextual Info: NT5DS32M16CS NT5DS64M8CS / NT5DS64M8CG NT5DS128M4CS 512Mb DDR SDRAM Feature z DLL aligns DQ and DQS transitions with CK transitions z DDR 512M bit, Die C, based on 90nm design rules z Double data rate architecture: two data transfers per clock cycle

Contextual Info: NT1GD72S4PC0FV/NT2GD72S4NCOFV 1GB: 128M x 72 / 2GB: 256M x 72 Low Profile Registered DDR SDRAM DIMM Preliminary 184pin Low Profile Registered DDR SDRAM DIMM Based on 128Mx4 DDR SDRAM C Die device Features • 184 Dual In-Line Registered Memory Module RDIMM