A54SX16P Search Results

54sx08

Abstract: THERMAL Fuse m20 tf 115 c
Contextual Info: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

CQFP 256 PIN actel

Contextual Info: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level

ACTEL BGA329

Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Contextual Info: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption

vhdl code for motor speed control

Abstract: ANTIFUSE
Contextual Info: Actel’s Antifuse FPGAs Programmable ASIC Solutions Space Electronics Communications Infrastructure e-Appliances The Antifuse Advantage Actel’s antifuse devices are low-cost, high-performance solutions for today’s logic designer. Ideal for integrating logic typically implemented in multiple CPLDs, PALs,

Contextual Info: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level

Contextual Info: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance

b23n20

Contextual Info: ^ c te -m v 2. 0 l 54SX Family FPGAs • • • • • 100%Resource Utilization with 100%Pin Locking 3.3VOperation with 5.0VInput Tolerance Very Low Power Consumption Deterministic, User-ControlIableTiming Unique, In-System Diagnostic and Debug capability with

THERMAL Fuse m20 tf 115 c

Abstract: 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 circuit diagram of motherboard W2-081 ac 171
Contextual Info: v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew

k16 a21

Abstract: 313-pin
Contextual Info: ^ c M J P relim inary • v 1 .1 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance Hi gh P e r f o r m ance • Low Power Consumption • 320 MHz Internal Performance • Deterministic, User-ControlIableTiming • 4.0 nsClock-to-Out Pi n-to-Pi n

THERMAL Fuse m20 tf 115 c

Abstract: 54SX16A actel fpga 54sx32 54SX32
Contextual Info: ^ c te l v 2 .0 54SX Family FPGAs L ea d in g Edge Pe rform an ce • 100% Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3V Operation with 5.0V Input Tolerance • 3.7 ns Clock-to-Out Pm-to-Pin • Very Low Power Consumption

6 pins IC cbe

Contextual Info: Æ c fe / -m v 2 .0 CorePCI Target 33/66 MHz P ro d u ct S um m ary In te n d e d U s e • High-Performance PCI Target Applications - 32-Bit, 66MHz. 3.3V - 32-Bit, 33MHz, 5V or 3.3V • Back-End Support for Synchronous DRAM, I/O

Contextual Info: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput

LRD12

Abstract: IRD12
Contextual Info: 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance High • Low Power Consumption Perform ance • 320 MHz I nternal Performance • Deterministic, User-ControlIableTiming • 4.0 ns Cl ock-to-Out Pin-to-Pin • Unique, In-System Diagnostic and Debug Facility with

CQ256

Abstract: CQ208 4PMX 4pm smd
Contextual Info: te /e • / Speed Grade JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, - 1 , - 2 , - 3 129 8,000 256 512 - — Yes Yes — — Yes PQ208 Std, - 1 , - 2 , - 3 129 8,000 256 512 — — Yes Yes — — Yes TQ144 Std, - 1 , - 2 , - 3 129 8,000

A54SX72

Contextual Info: ^ c te l P r e lim in a r y v1„0 CorePCI Target+DMA Master 33/66MHz P ro d u ct S um m ary Section In te n d e d U s e • High-Performance 33MHz or 66MHz PCI Target+DMA Master Applications Page I/O Signal Descriptions 415 Supported Comm ands 418 Device Utilization

Contextual Info: Preliminary v 1 .2 54SX Family FPGAs RadTolerant and HiRel Features • 100%Resource Utilization with 100%Pin Locking Rad T o lera nt 54SX Family • Mixed Voltage Support— 3.3V Operation with 5.0V Input • TestedTotal Ionizing Dose TID Survivability Level