825MIL Search Results

Contextual Info: IBM0164165B IBM0164165P 4M x 16 13/9 EDO DRAM Features • 4,194,304 word by 16 bit organization Dual CAS Byte Read/Write • Single 3.3 ± 0.3V power supply Performance: -50 • Extended Data Out Hyper Page Mode CAS before RAS Refresh - 4096 cycles/Retention Time

Contextual Info: IBM0116165 IBM0116165M IBM0116165B IBM0116165P 1 M x 16 12/8 EDO DRAM Features • 1,048,576 word by 16 bit organization • Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply • Standard Power SP and Low Power (LP) • 4096 Refresh Cycles - 64 ms Refresh Rate (SP version)

Contextual Info: 16Mbit Synchronous DRAM Series ♦HYUNDAI HY57V164010- 4Mx4bit Synchronous DRAM HY57V168010- 2Mx8blt Synchronous DRAM HY57V161610- 1Mx16bit Synchronous DRAM DESCRIPTION The HY57V164010, HY57V168010, HY57V161610 Programmable options include the length of are high speed 3.3 Volt synchronous dynamic RAMs

K4S161622H-UC60

Abstract: K4S161622H-UC70 uc60 K4S161622H-UC80 K4S161622H K4S161622H-UC55
Contextual Info: K4S161622H CMOS SDRAM 16Mb H-die SDRAM Specification 50 TSOP-II with Pb-Free RoHS compliant Revision 1.4 August 2004 Samsung Electronics reserves the right to change products or specification without notice. Rev 1.4 August 2004 K4S161622H CMOS SDRAM Revision History

Contextual Info: ESMT M52D16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 1, 2 & 3 Burst Length (1, 2, 4, 8 & full page)

Contextual Info: K4S161622D CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.5 September 2000 Samsung Electronics reserves the right to change products or specification without notice. Rev 1.5 Sep. '00 K4S161622D CMOS SDRAM Revision History

Contextual Info: K4S161622D-TI/P CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Industrial Temperature Revision 1.0 June 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 Jun . 1999 K4S161622D-TI/P

M12S16161A

Abstract: M12S16161A-7BG M12S16161A-7TG
Contextual Info: ESMT M12S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 2 & 3

M52S16161A

Abstract: M52S16161A-10TG M52S16161A-8BG M52S16161A-8TG
Contextual Info: ESMT M52S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z z z GENERAL DESCRIPTION 2.5V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 1, 2 & 3 Burst Length (1, 2, 4, 8 & full page)

HY57V161610D

Abstract: HY57V161610DTC-10I HY57V161610DTC-55I HY57V161610DTC-6I HY57V161610DTC-7I
Contextual Info: HY57V161610D 2 B a n k s x 5 1 2 K x 1 6 B it S y n c h r o n o u s D R A M DESCRIPTION THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of

Contextual Info: M12L16161A 2Q SDRAM 512K x 16Bit x 2Banks Synchronous DRAM GENERAL DESCRIPTION FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page)

HY57V161610E

Abstract: HY57V161610ET-10I HY57V161610ET-15I HY57V161610ET-55I HY57V161610ET-5I HY57V161610ET-6I HY57V161610ET-7I HY57V161610ET-8I HY57V161610ET-I
Contextual Info: HY57V161610ET-I 2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.

M52D16161A-10BG

Abstract: M52D16161A M52D16161A-10TG
Contextual Info: ESMT M52D16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z z z GENERAL DESCRIPTION 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 1, 2 & 3 Burst Length (1, 2, 4, 8 & full page)

Contextual Info: KM416S1120D CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.4 May 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 May. 1999 KM416S1120D CMOS SDRAM Revision History

IBM0164405B16M

Abstract: IBM0164405P16M GA15 514300
Contextual Info: Discontinued 8/98 - last order; 12/98 last ship IBM0164405B16M x 413/11, 3.3V, EDO. IBM0164405P16M x 413/11, 3.3V, LP, SR, EDO. IBM01644F5B 16M x 8 13/11 Stacked DRAM Features • 16,777,216 word by 4 bit organization by 2 high • Single 3.3 ± 0.3V power supply

Contextual Info: KM416S1020C CMOS SDRAM 1Mx 16 SDRAM 5 12K X 16bit X 2 Banks Synchronous DRAM LVTTL Revision 0.6 September 1998 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.6 Sep. 1998 ELECTRONICS KM416S1020C CMOS SDRAM

Contextual Info: M52S16161A 2J Mobile SDRAM 512K x 16Bit x 2Banks Mobile Synchronous DRAM FEATURES GENERAL DESCRIPTION 2.5V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page)

IBM01181651M

Abstract: IBM0118165B1M IBM0118165M1M IBM0118165P1M ibm 9398
Contextual Info: Discontinued 9/98 - last order; 3/99 last ship IBM01181651M x 1610/10, 5.0V, EDOMMDD59DSU-001014332. IBM0118165P1M x 1610/10, 3.3V, EDO, LP, SRMMDD59DSU-001014332. IBM0118165M1M x 1610/10, 5.0V, EDO, LP, SRMMDD59DSU-001014332. IBM0118165B1M x 1610/10, 3.3V, EDOMMDD59DSU-001014332.

HY57V161610FTP

Abstract: HY57V161610F-Series
Contextual Info: 16Mb Synchronous DRAM based on 512K x 2Bank x16 I/O Document Title 2Bank x 512K x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Feb. 2006 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

M52D16161A

Abstract: M52D16161A-10BG M52D16161A-10TG cke 2009 amp
Contextual Info: ESMT M52D16161A Mobile SDRAM 512K x 16Bit x 2Banks Mobile Synchronous DRAM FEATURES z z z z z z z z z z z GENERAL DESCRIPTION The M52D16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology.

M52D16161A

Contextual Info: ESMT M52D16161A Operation Temperature Condition -40°C~85°C Mobile SDRAM 512K x 16Bit x 2Banks Mobile Synchronous DRAM FEATURES z z z z z z z z z z z GENERAL DESCRIPTION 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs

M12S16161A

Abstract: M12S16161A-7BG M12S16161A-7TG
Contextual Info: ESMT M12S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 2 & 3

Contextual Info: HY57V161610D 2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of

Contextual Info: ESMT M12D16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 1, 2 & 3 Burst Length (1, 2, 4, 8 & full page)