74LS125 N Search Results

74ls gate symbols

Abstract: TTL 74ls125 74125 ic 74LS125 74125 logic diagram 74LS series logic gate symbols 74125 TTL 74ls126 74LS366 TTL 74126
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D65 54/7413, 54LS/74LS13 Vcc NC R R R fü| FÖI f71 r«l D66 54/74125, 54LS/74LS125 D67 54/74126, 54LS/74LS126 Vcc Vcc EEp ^ ] III III liJ Lil 111 Lil 111 QND y y O E D O rn m E D O E D O R R R R Fol R |7|

CI 7408

Abstract: CI 74LS08 TTL 74ls21 74LS21 7407 connection diagram 54LS CI 7413 7432 TTL fairchild 74LS125 7408 and
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L - T T L D65 54/7413, 54LS/74LS13 Vcc NC R R R fü| FÖI f71 r«l D66 54/74125, 54LS/74LS125 D67 54/74126, 54LS/74LS126 Vcc Vcc äJ QND E D68 54LS/74LS365 j y E D O 3X 5 rn m D O E D D O E D O IPTJ? ~ ? f i r

TTL 74ls125

Abstract: 74ls125 74125 logic diagram 74LS126 74LS366 74ls368
Contextual Info: FAIRCHILD DIGITAL TTL Logic/Connection Diagram 2 Packages(3) 9386 (8242) D94 3I,6A,9A D25 4L,6B,9B — D26 3I,6A,9A — D27 3I,6A,9A 54S/74S51 D28 3I,6A,9A High Speed Schottky 54S/74S 3 ns/19 mW 74LS266 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW

55GND

Abstract: 74LS125 12S2B BUS13 CC-249 of 74ls125 74LS125 DATASHEET BT8952 BUS12 BUS14
Contextual Info: A B C D REVISIONS ZONE LTR DATA[0:7] DESCRIPTION APPROVED DATE A B INITIAL RELEASE 95-10639 INCORP ECN # 95-11049 C INCORP ECN # +5V -12V 1 J6 J6 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30

74LS125

Abstract: 74HC125
Contextual Info: SANYO SEMICONDUCTOR CORP 15 E D I 7 ^ 7 0 7 ^ DDDSh73 c J T :4 V 2 .1 LG74HC12& 3003A CM O S High-Speed Standard Logic LC74H C Series Quad 3-State Bus Buffer £ *2029A Features • The LC74HC125 consists of 4 identical noninverting buffers with 3-state outputs.

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51
Contextual Info: FAIRCHILD DIGITAL TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Item 9000 Series 8 ns/10 mW (Cont'd) Function’11 SSI FUNCTIONS 5 't/I

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gate symbols 74ls gate symbols 74LS series logic gates 74H55 74125 ic 74LS126 TTL 74125 74H62 buffer 74ls series logic gates
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 D34 54LS/74LS55 V cc Vcc 1 1 D35 S4H/74H61 r D36 9006, 54/7460, 54H/74H60 Vcc i ifi nil n iiöirài n r a r a rni fsi m m =¿0 J 1 i r Lil liJ 111 Lii 111 lu HJ QND D37 54H/74H62 D39 96106 Vcc

trigger 74114

Abstract: 74114 IC 7404 74LS13 74ls04 hex inverter gates IC 7413 schmitt trigger 7413 rs 7410 7438 IC 7422
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L - T T L D65 54/7413, 54LS/74LS13 Vcc NC Vcc R R R fü| FÖI f71 r«l QND E D68 54LS/74LS365 j E D Vcc O rn m D O E D D O E D O IPTJ? ~ ? i f r h O E lil lil lil 111 liJ liJ Id O OND E D D O QND D70 54LS/74LS367

IC TTL 7432

Abstract: 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn

ALU IC 74181

Abstract: ic 74LS83 IC 74181 alu 74181 alu IC 74181 ic 7485 74LS series logic gate symbols ALU 74181 ttl 74181 ic 7485 4 bit comparator
Contextual Info: FAIRCHILD DIGITAL TTL o o 'S « z _o- c Power Dissipation mW Typ Logic/Connection Diagram Package(s) E £ Description* Function DEVICE NO. ARITHMETIC OPERATORS 1 47 105 D100 3I,6A,9A » ffl 1 Adder 2 Adder 9304 Dual 1-Bit with Carry 2 26 150 D101 3I,6A,9A

Contextual Info: /5 T S C S -T H O M S O N ^ 7 # « [* [M [I0 = i g ^ (Q )R l § M54/74HC125 M54/74HC126 QUAD BUS BUFFERS (3-STATE) • HIGH SPEED tpD = 10 ns (TYP.) at VCc = 5V ■ LOW POWER DISSIPATION lCc = 4 ¡iA (MAX.) at T A = 2 5 °C ■ HIGH NOISE IM M U N ITY V n ih = V N|L = 2 8 % Vc c (MIN.)

fusistor

Abstract: TP3210 5vdc relay Deutsch Relays 74ls125 application 74LS125 DATASHEET DS2E-5V THE SLIM POWER RELAY telephone switching equipment deutsch relay
Contextual Info: National Semiconductor System Brief 100 May 1990 TL F 10850 – 1 SYSTEM DESCRIPTION Subscriber linecards are designed to interface the analog subscriber line to a PCM highway in a Digital Central Office or a Digital Loop Carrier DLC channel bank or remote concentrator systems Subscriber Line Interface Module

4Y103g

Abstract: TC74HC125AFN TC74HC125AP 126ap TC74HC125AF TC74HC126AF TC74HC126AP V31G
Contextual Info: TOSHIBA TC74HC125AP/AF/AFNJ 26AP/AF TO SH IBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74HC125AP, TC74HC125AF, TC74HC125AFN TC74HC126AP, TC74HC126AF TC74HC125AP/AF/AFN TC74HC126AP/AF QUAD BUS BUFFER QUAD BUS BUFFER Note The JEDEC SOP (FN) is not available in

4g36

Abstract: TC74HC125AP
Contextual Info: TOSHIBA TC74HC125AP/AF/AFNJ 26AP/AF TO SH IBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74HC125AP, TC74HC125AF, TC74HC125AFN TC74HC126AP, TC74HC126AF TC74HC125AP/AF/AFN TC74HC126AP/AF QUAD BUS BUFFER QUAD BUS BUFFER Note The JEDEC SOP (FN) is not available in

Contextual Info: GD54/74LS125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS Description Pin Configuration This device contains 4 buffers with 3-state out­ puts and is provided with an output control input C which is independent for each buffer. Vcc 4C 4A 4Y 3Ç 3A 3Y 14

ALU IC 74181

Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn

Contextual Info: SbE • J> 7T2T237 OCmfibG ÎGT ■ S G T H SCS-THOMSON Moœ itie«Mï®Ë§ M54/74HC125 M54/74HC126 ty 3 — 2 { S G S-THOMSON QUAD BUS BUFFERS 3-STATE ■ HIGH SPEED tpo = 10 ns (TYP.) at V c c = 5V ■ LOW POWER DISSIPATION lcc = 4 (MAX.) at TA = 25°C

hct125

Abstract: TTL 74ls125 74HCT125 M54HCTXXXF1R M74HCTXXXB1R M74HCTXXXC1R M74HCTXXXM1R m74hct125
Contextual Info: M54/74HCT125 M54/74HCT126 QUAD BUS BUFFERS 3-STATE . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE

M74HC125

Contextual Info: M54/74HC125 M54/74HC126 SGS-THOMSON 10 QUAD BUS BUFFERS 3-STATE HIGHSPEED tPD = 8 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Ice = 4 nA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS BALANCED PROPAGATION DELAYS tP L H = t P H L SYMMETRICAL OUTPUT IMPEDANCE

HCT125

Contextual Info: r z z Ä 7 # S G S -T H O M S O N M lM a [ iO T ö K S M 5 4 /7 4 H C T 1 25 M 5 4 /7 4 H C T 1 2 6 QUAD BUS BUFFERS (3-STATE) • HIGHSPEED tPD = 12 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 4 |iA (MAX.) AT 25 °C ■ OUTPUT DRIVE CAPABILITY

7450 ttl

Abstract: 74LS series logic gates 3 input or gate 74LS126 74LS125 74LS51 74LS series logic gates 7454 74H55 7453 logic diagram ic 74125
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D27 9005, 54/7450, 54H/74H50 D26 54H/74H52 D25 9S42 Vcc R FI FI R R R R R r r r r r r r ^ LÜliJ LULlIET'til LilGND r r - lU lil lil liJ'lil L iitn GND D30 54/7454, 54H/74H54 D29 9008, 54/7453, 54H/74H53 D28

TC74HC125AFN

Contextual Info: TOSHIBA TC 74H C 125A P /A F/A FN ,126A P /A F TO SHIBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74HC125AP, TC74HC125AF, TC74HC125AFN TC74HC126AP, TC74HC126AF TC74HC125AP/AF/AFN TC74HC126AP/AF QUAD BUS BUFFER QUAD BUS BUFFER Note The JEDEC SOP (FN) is not available in

Contextual Info: GD54/74LS125A QUADRUPLE BUS BUFFER GATES W ITH 3-STATE OUTPUTS Description This device contains 4 buffers with 3-state out­ puts and is provided with an output control input C which is independent for each buffer. Pin Configuration Vcc 4C 4A 4Y 3C 3A 3Y 14

74HC125A

Abstract: TC74HC125AFN
Contextual Info: TOSHIBA TC 74H C 125A P /A F/A FN ,126A P /A F TO SHIBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74HC125AP, TC74HC125AF, TC74HC125AFN TC74HC126AP, TC74HC126AF TC74HC125AP/AF/AFN TC74HC126AP/AF QUAD BUS BUFFER QUAD BUS BUFFER Note The JEDEC SOP (FN) is not available in