74LS139 Search Results

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H 74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

74191 8 bit

Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74LS190 PIN diagram

Abstract: ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

7448 decoder

Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8

transistor d133

Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

Contextual Info: LS TTL DN74LS Series 74LS139 74LS139 Dual 2 -lin e to 4 -lin e Decoders / Demultiplexers H Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals. • Features

Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _

SP74SC139N

Abstract: 74ls139 decoder pin configuration 74LS139 SP74SC139F E332A
Contextual Info: / SP74SC139 DECODER/DEMULTIPLEXER PIN CO NFIGURATIO N 1G [ T v cc 1A [T Ï3 2G FEATURES • Designed for high performance memory decoders in microprocessor sytems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin compatible with 74LS139

74LS139

Abstract: 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 93L21 N74LS139D N74LS139N
Contextual Info: 74LS139, S139 Signetics Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x e r Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

74LS139PC

Abstract: 74LS139P 74LS139DC
Contextual Info: ;'1 NATIONAL SEMICOND -CLO.GIO OSE D | bSDllPS 00b3fll? D | 139 139 T-66-21-55 CONNECTION DIAGRAM P IN O U T 54S/74S139 54LS/74LS139 A o a [I i s ] Eb A la [ 7 Î 7 ] Aob Öoa [ T 75] 1 2 ]Ö 0 b Ö 2a [ ? T ijö ib Ô 3 a [T 10] 5 2 b [? ~9~1 0 3 b DESCRIPTION — The *139 is a high speed dual t-of-4 decoder/demulti­

74HC139M

Abstract: 74hc139n
Contextual Info: A s e m I R C i c o n H d u S eptem ber 1983 I L D Revised February 1999 c t o r MM74HC139 Dual 2-To-4 Line Decoder equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and General Description The M M 74H C 139 deco d e r utilizes advanced silicon-gate

pin diagram of ic 74ls139

Abstract: LS 74LS139 74LS139 74ls139 decoder 74ls139 decoder pin configuration decoders 3*8
Contextual Info: 7 4 LS1 3 9 , S139 Decoders/Demultiplexers S ig n e t ic s Dual 1-of-4 Decoder/Demultiplexer Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY ENABLE AT 2 LOGIC LEVELS TYPICAL SUPPLY CURRENT (TOTAL) 74LS139 19ns 6.8mA 74S139 6ns 60mA

74LS139

Abstract: of ic 74ls139 5101 fg
Contextual Info: <8> M O T O R O L A SN54/74LS139 D E S C R I P T I O N — The L S T T L / M S I S N 5 4 L S / 7 4 L S 1 3 9 is a high speed Dual 1-of*4 Decoder/Demultiplexer. T he device h as two independent decoders, each accepting tw o inputs and providing four mutually

74ls139 decoder pin configuration

Abstract: SP74HCT139N 74LS139 SP74HCT139J 74LS139 pin configuration with
Contextual Info: SPI SP74HCT139 DECODER/DEMULTIPLEXER FEATURES • Designed for high performance memory decoders in microprocessor systems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin com patible with 74LS139 ■ SPI CMOS technology

demultiplexer truth table

Abstract: 74ls139 datasheet 74ls139 decoder SN54/74LS139 transistor motorola 236 LS139 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS139 application
Contextual Info: SN54/74LS139 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

74LS139

Abstract: 74ls gate symbols 74LS 1 into 16 demultiplexer circuit diagram using 1 i AM25LS LS 74LS139 Am25LS139
Contextual Info: Am25LS139 • Am54LS/74LS139 Dual 2-Line To 4-Line Decoder/Demultiplexer D IS T IN C T IV E C H AR AC TER ISTIC S FUNCTIONAL DESCRIPTION • • The Am 25LS 139 is a du al 2 -lin e to 4 -lin e d e co d e r/d e m u lti­ p le x e r u n it fa b r ic a te d u s in g a d v a n c e d L o w -P o w e r

74LS139

Abstract: S139
Contextual Info: 74LS139, S139 Signetìcs Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x er Product Specification Logic Products FEA TUR ES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

Contextual Info: Am25LS139 • Am54LS/74LS139 Dual 2-Line To 4-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S FUNCTIONAL DESCRIPTION • • T h e A m 2 5 L S 1 3 9 is a du al 2 -lin e to 4 -lin e d e c o d e r/d e m u lti­ p le x e r u n it f a b r ic a te d u s in g a d v a n c e d L o w - P o w e r

Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The 74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

DN74LS139

Abstract: MA161
Contextual Info: I LS T T L DN74LS Series 74LS139 74LS139 Dual 2 - lin e to 4 - lin e D ecoders / D em ultiplexers I Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals.

74LS139

Abstract: M16A M16D MM74HC139 MM74HC139M MM74HC139MTC MM74HC139SJ MTC16 diode D254
Contextual Info: Revised February 1999 E M IC O N D U C T O R T M MM74HC139 Dual 2-To-4 Line Decoder General Description equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and T he M M 74H C 139 d ecoder utilizes advanced silicon-gate

74LS138

Abstract: 7443 ttl 74155 ttl 74191 7443 TTL 74ls138 74LS139 74LS191 74ls138 fairchild TTL 74145
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74LS190 PIN diagram

Abstract: presettable digital clock ttl 74191 Fairchild 74190 74LS191 74155 D130 74192 74ls192 pin diagram of 74163
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74191 8 bit

Abstract: D flip-flop 74175 pin 74LS152 74155 D134 D132 74155 PIN DIAGRAM 7442 logic diagram D133 93L21
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8