74LS13 Search Results

M74LS136P

Abstract: 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR
Contextual Info: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2 -IN P U T EXC LU SIVE OR GATES W IT H OPEN COLLECTOR O UTPU TS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H 74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

DDR Schaltkreise

Abstract: DL014D DL132D 74LS132N Deutschen Demokratischen Republik DSAGER00016 74ls014 26713
Contextual Info: inn]D[klP3is ] ^ i0 ^ ^ 3 ls,Q n S ' DL 014 D DL 132 D Internationale Vergleichstypen; SN 74L S 014 N SN 74LS132 N Schaltkreise in Low -pow er-S chottky-Tschnologie DL 0 14 D 6 Schm itt-Trigger-Inverter Y = Ä DL 132 D 4 S chm itt-Trigger NAND-Gatter m it je 2 Eingängen

74191 8 bit

Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74LS190 PIN diagram

Abstract: ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

7448 decoder

Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8

transistor d133

Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

TTL LS 7406

Abstract: el 7406 74l804 ls 7404 7404 ls 74114 ic 74132 IC 7404 IC TTL 7402 TTL IC 7405
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I Vcc E RRRRRRRFl LiJ ikj Lil l±J UJ LsJ IzJ GND LU D11

Contextual Info: 74LS136 LS TTL DN74LS Series 74LS136 Quad 2 - input E xclusive OR G ates with Open C ollector Outputs • Description P-1 DN 74LS136 contains four 2-input exclusive OR gate circuits w ith open collector outputs. ■ • • • • Features “Wired” AND capability

Contextual Info: LS TTL DN74LS Series 74LS139 74LS139 Dual 2 -lin e to 4 -lin e Decoders / Demultiplexers H Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals. • Features

Contextual Info: Am25LS138 • Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • Inverting and non-inverting enable inputs • A m 2 5 L S devices offer the following improvements over Am 54/74LS

Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _

LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
Contextual Info: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding

SP74SC139N

Abstract: 74ls139 decoder pin configuration 74LS139 SP74SC139F E332A
Contextual Info: / SP74SC139 DECODER/DEMULTIPLEXER PIN CO NFIGURATIO N 1G [ T v cc 1A [T Ï3 2G FEATURES • Designed for high performance memory decoders in microprocessor sytems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin compatible with 74LS139

74LS139

Abstract: 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 93L21 N74LS139D N74LS139N
Contextual Info: 74LS139, S139 Signetics Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x e r Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

TTL 74ls133

Abstract: 74ls133 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS133 13-INPUT NAND GATE 13-INPUT NAND GATE VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 GND LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN

74ls138 truth table

Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
Contextual Info: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­

IC 74LS14

Abstract: 74ls14 74LSxx ic 74ls13
Contextual Info: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

74LS132

Contextual Info: MOTOROLA SN54/74LS132 QUAD 2-INPUT SCHMITT TRIGGER NAND GATE The S N 54/74LS 132 contains four 2-Input NAND Gates which accept stan­ dard TTL input signals and provide standard TTL output levels. They are ca­ pable of transforming slowly changing input signals into sharply defined, jitterfree output signals. Additionally, they have greater noise margin than

Contextual Info: <8 > M OTOROLA SN54/74LS133 mrnirnmrrirnram -1 r u w -1 u 1 13-1NPUT NAND GATE 1 Ù L ìJ L ì J L L J I Ì J L l I LO W POW ER SCH O TTK Y J Suffix — Case 620-09 Ceramic N Suffix — Case 648-08 (Plastic) GUARANTEED OPERATING RANGES S YM B O L PARAMETER

74LS133

Abstract: truth table NOT gate 74
Contextual Info: M MOTOROLA SN54/74LS133 13-INPUT NAND GATE 13-IN P U T NAND GATE VCC MRrïïirïïiRirïïir^im LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 L U L iJ ll J L i J L i J L iJ LULjJ GND N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 5 ORDERING INFORMATION

74LS137

Abstract: aag2
Contextual Info: <8> M O TO R O LA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC YÛ Y1 Y2 Y3 Y4 Y5 Y6 pisi |~i?1 |~ÌT| HT! fiil f~M~| [~iÖ1 [~9~|

74LS13

Abstract: 74LS14 751A-02 trigger schmitt 74 14 ttl 74ls14
Contextual Info: SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS / 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

Contextual Info: LS TTL DN74LS Series 74LS13 74LS13 &MHIS13 Dual 4 -input P o sitiv e NAND S ch m itt-T riggers H D escription P-1 DN 74LS13 contains tw o 4-input positive isolation NAND circuits w ith Schm itt triggers. • Features • • • • • Ideal for w aveform shaping