74LS30 Search Results

741s

Abstract: CI 741S DN74LS30 MA161
Contextual Info: LS TTLDN74LS Series 74LS30 74LS30 £>to 7a LS 30 8 - input P o sitiv e N AN D Gates B Description P-1 DN 74LS30 contains one 8-input positive isolation NAND gate circuit. • Features • • • • Low pow er consum ption Pd = 2.5m W typical High speed ( t pd = 1 In s typical)

751A-02

Abstract: TTL 74ls30 FAST AND LS TTL motorola ceramic dual in-line case 74ls30 datasheet
Contextual Info: SN54/74LS30 8-INPUT NAND GATE 8-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

TTL LS 7406

Abstract: el 7406 74l804 ls 7404 7404 ls 74114 ic 74132 IC 7404 IC TTL 7402 TTL IC 7405
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I Vcc E RRRRRRRFl LiJ ikj Lil l±J UJ LsJ IzJ GND LU D11

74LS30PC

Abstract: 74LS30 74LS30P 7430DC
Contextual Info: 30 CO NNECTIO N DIAGRAMS PINO UT A 54/7430 o/ô //7 54H/74H30 ò /q /s o W54S/74S30/ , \/54LS/74LS30 O Vcc d 8-INPUT NAND GATE E E E m Œ ]Ö ]N C [7 I] 1 3 ]n C 13 U gnd ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%,

truth table NAND gate 74

Abstract: 74LS30 751A-02
Contextual Info: M MOTOROLA, SN54/74LS30 8-INPUT NAND GATE 8-tNPUT N A N D GATE vcc fui r nji nyi nói nn LOW POWER SCHOTTKY it i J SUFFIX CERAMIC CASE 632-08 14 GND 1 N SUFFIX PLASTIC CASE 646-06 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

Contextual Info: G054/74LS30 8-INPUT POSITIVE NAND GATE Description This device contains a single 8-input NAND gate and performs the following Boolean functions in positive logic. Y = A • Bj C E • F_G _H or Y = Â + B + C + D + Ë + F + 3 + H Function Table O U TP U T

PIN CONFIGURATION OF 74LS30

Abstract: TTL 7430 7430 ic IC 7430 7430 Eight-Input NAND Gate 7430 pin configuration 7430 74ls30 equivalent 8 input nand gate 7430
Contextual Info: Signetics I 7430, LS30 Gates Eight-Input NAND Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7430 11ns 2mA 74LS30 11ns 0.5mA ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to +70°C PACKAGES

Contextual Info: LS TTL DN74LS Series 74LS30 DN741S30 £1074 IS 3 0 8 - input Positive NAND Gates H Description P-1 DN 74LS30 contains one 8-input positive isolation NAND gate circuit. • Features • • • • Low pow er consum ption P^ = 2.5mW typical High speed ( t pd = 1 In s typical)

TTL LS 7407

Abstract: CI 7407 CI 7402 TTL LS 7402 ls 7408 TTL 74s02 CI 74LS02 74LS27 TTL 7425 TTL 74ls02
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 D9 54S/74S134 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I E RRRRRRRFl li lli lli lli J lill ill ill iJGND

74LS30

Abstract: TTL 74ls30 751A-02 truth table nand gate
Contextual Info: SN54/74LS30 8-INPUT NAND GATE 8-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

74LS30

Abstract: 74ls gate symbols 54LS 74LS
Contextual Info: GD54/74LS30 8-INPUT POSITIVE NAND GATE Description This device contains a single 8-input NAND gate and performs the following Boolean functions in positive logic. Y = A B C - D - E I - , ü _H or _ Y = Â + B+ C + D+ Ë + F + G + H Function Table O U TP U T

Contextual Info: M M O T O R O L A SN54/74LS30 _k l r r n r*i 8-INPUT N A N D G ATE L i LiJ LU lil -L iJ Lj L I LOW PO W ER SCM O TTKY J Suffix — Case 632*08 (Ceramic) N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES S YM B O L MIN TYP MAX UNIT V cc Supply Voltage

TTL 74ls30

Abstract: 74LS30 truth table NAND gate 74 all gate ic data 74
Contextual Info: fò MOTOROLA SN54/74LS30 8-INPUT NAND GATE 8-IN P U T NAND GATE Vcc LOW POWER SCHOTTKY ini [ïïi rmrmr^i m rn J SUFFIX s C E R A M IC C A SE 632-08 LU LU LU LU LU LU Ll I GND N SUFFIX .J ^ P ÏÏ oüiSE. D SUFFIX soie C A SE 751A-02 5 ORDERING INFORMATION

7430 ic

Abstract: IC 7430 PIN CONFIGURATION OF 74LS30 7430 LS 7430
Contextual Info: Signelics | 74 3 0 , LS30 Gates Eight-Input NAND Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7430 11ns 2mA 74LS30 11ns 0.5mA ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5% ; T a = 0°C to + 70°C PACKAGES

74LS30PC

Abstract: 7430DC 7430PC 74H30DC 74S30PC 5430DM 74H30PC 74LS30DC 74S30DC
Contextual Info: 30 C O N N E C T IO N D IA G R A M S P IN O U T A 54/7430 o/ô //7 54H/74H30 / ;, W54S/74S30/ , \/54LS/74LS30 ^ 8 -IN P U T N A N D G A T E O ' O R D E R IN G C O D E : See S e c tio n 9 PIN PKG S OUT C O M M E R C IA L G R AD E M IL IT A R Y G R AD E V cc = + 5 .0 V ±5%,

S54LS30F

Abstract: 74LS30 N7430F N7430N N74H30F N74H30N N74LS30F N74LS30N S5430F S54H30F
Contextual Info: PIN CONFIGURATIONS 54/7430 54H/74H30 54LS/74LS30 ORDERING CODE See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES “ 5V - 5%; T A = 0°C to *70°C PACKAGES PIN CON F. P lastic DIP Fig. A Fig. A N7430N • N74H30N 74LS30N

Contextual Info: GD54/74LS30 8-INPUT POSITIVE NAND GATE Description This device contains a single 8-input NAND gate and performs the following Boolean functions in positive logic. Y = A B C D E F G H or Y=Â+B+C+D+Ë+F+S+H Function Table OUTPUT INPUTS A THRU H Y All inputs H

TTL LS 7407

Abstract: TTL 7427 TTL 7402 LS 7430 LS 7402 74LS02 74LS30 ttl 7407 d1554 TTL 74s02
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I 5T5 R Fl R R R FI FI aia LU 111 111 Li] lij lil L J

hd74lsoop

Abstract: 74LSOO 74LSOO AND gate A2210
Contextual Info: H D 74LS30. 8-input Positive NAND Gate •PIN ARRANGEM ENT ■CIRCUIT S C H EM A T IC ■ E L E C T R IC A L C H A R A C T E R IS T IC S Ta= - 2 0 - + 75°C Item T est Conditions Symbol VlH Input voltage V lL VOH Vcc = 4.75V , V,/l = 0 .8 V ,/o h = -4 0 0 M

LS30

Abstract: PIN CONFIGURATION OF 74LS30 2313m TTL 7430 7430 Eight-Input NAND Gate 74LS TTL 1N3064 1N916 74LS 74LS30
Contextual Info: Signetics | 7430, LS30 Gates Eight-Input NAND Gate Product Specification Logic Products TYPE TYPICAL SUPPLY CURRENT TOTAL TYPICAL PROPAGATION DELAY 7430 11ns 2mA 74LS30 11ns 0.5mA ORDERING CODE COMMERCIAL RANGE VCc = 5V ±5% ; T a = 0°C to + 70*0 PACKAGES

N74LS301D

Contextual Info: Philips Components-Signetics 74LS301 Document No. 8 5 3 -0 1 2 7 ECN No. 8 64 8 7 Date of Issue N ove m b e r 11, 1986 Status P ro du ct S p ecification 256-bit TTL bipolar RAM M em ory P ro du cts PIN CONFIGURATION DESCRIPTION FEATURES The 74LS301 is a R ead/W rite m em ory

74LS30PC

Contextual Info: NATIONAL SEMICOND -CLOGIO G5E D I b 5 0 1 1 2 3 ou CO NN ECTIO N DIAGRAMS PINO UT A 54/7430 54H/74H30 54S/74S30 54LS/74LS30 8-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERC IAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0 °C to +70° C

74LS301

Abstract: EE-S5 LS301 N74LS301 N74LS301F N74LS301N S54LS301 S54LS301F S54LS301G S54LS301W
Contextual Info: MAY 1982 BIPOLAR M E M O R Y DIVISION 256-BIT TTL RAM 256 x 1 54/74LS301 (P .C .) DESCRIPTION + 7 5°C ) a n d th e m ilit a r y t e m p e ra tu r e ra n g e ( - 5 5 °C t o + 125°C). T h e y a re s p e c ifie d as: T h e 54/7 4 L S 3 0 1 is a R e a d /W r ite m e m o ry

DN74LS30

Abstract: MA161
Contextual Info: !» LSTTL DN74LS Series 74LS30 74LS30 8-input P ositive NAND Gates • Description P-1 D N 74LS30 contains one 8-input positive isolation NAND gate circuit. ■ Features • • • • Low pow er consum ption P<j = 2.5mW typical High speed ( t pd = 1 In s typical)