74LS113 Search Results

74S113D

Abstract: 74LS113D
Contextual Info: 113 C O N N E C T IO N DIAGRAM P IN O U T A 548/748113 * 54LS/74LS113 ö / / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP D ESCRIPTION — T h e ’ 113 o ffe rs in d iv id u a l J, K, Set an d C lo c k inputs. W hen the c lo c k g o e s H IG H the in p u ts are e n a b le d and data m ay be entered.

74LS113

Abstract: C0056
Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces

74LS113

Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Contextual Info: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro ­

74LS113A

Abstract: tp 2123
Contextual Info: MITSUBISHI LSTTLs M 7 4LS 113 A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

74LS113

Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set S d input, w hen LOW, forces

74LS113

Abstract: S113 equivalent
Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set Su input, when LOW, forces

74LS113A

Contextual Info: AA M O T O R O L A SN54/74LS113A D E S C R IPT IO N — The S N 5 4 L S /7 4 L S 1 13A offers individual J, K, set, and clock inputs. These m onolithic dual flip-flops a re designed so that w h e n th e clock goes HIGH, th e inputs a re enabled and data w ill be

74LS113A

Abstract: SN54LSXXXJ truth table NOT gate 74 751A-02 SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K

JK flip flop IC

Abstract: JK flip flop IC diagram M74LS113AP Toggle flip flop IC 20-PIN M74LS112AP
Contextual Info: M ITSU B IS H I L S T T L s 74LS113AP D U A L J-K N E G A T IV E E D G E - T R IG G E R E D F L I P F L O P W IT H S E T DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

truth table NOT gate 74

Abstract: 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN t flip-flop 74LS113A
Contextual Info: SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K

74LS113A

Contextual Info: <g MOTOROLA. SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K

74LS113

Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a d u a l J -K n e g a tive edg e trig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t and C lo c k inp u ts. T h e a s y n c h ro ­

74S113PC

Abstract: 54S113DM
Contextual Info: 1 NATIONAL SEfHCOND -CLOGIO DEE D I tiSGllSE DGbBTfii T T ~ *f¿ - 0 7 -0 7 Fl3 CO N N ECTIO N DIAGRAM PINO UT A 54S /74S 113 54LS /74LS113 D UA L JK E D G E -T R IG G E R E D FLIP-FLOP D ESC R IP TIO N — T h e '1 13offers individual J , K, Set and Clock inputs. When

74LS113

Contextual Info: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro­ nous S et Sp input, when LO W , forces

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108

Contextual Info: _ Sb E D • 7*^237 GOSSflMb 6 3 1 ■ S G T H _ / S T S C S -m O M S O N ^ 7 # H D ^ L [ l © ™ K 3D©i S M 5 4 H C 1 13 M 7 4 H C 113 T -M -0 7 -O 7 DUAL J-K FLIP FLOP WITH PRESET G S-THOMSON ■ HIGH SPEED fMAX= 64 MHz Typ. at V c c = 5V

k2645

Abstract: k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417
Contextual Info: 1 BHIAB Electronics Du som söker besvärliga IC & transistorer, börja Ditt sökande hos oss – vi har fler typer på lager än man rimlingen kan begära av ett företag Denna utgåva visar lagerartiklar men tyvärr saknas priser och viss information Men uppdatering sker kontinuerligt

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC113P/FP/DP DUAL I -K F L IP -F L O P WITH S E T DESCRIPTION T he M 7 4 H C 1 1 3 is a sem ico n d u cto r integrated circu it co n ­ PIN CON FIGURATIO N TOP VIEW sistin g of of tw o n e g a tiv e -e d g e trig g ered J - K flip flops with

SKIIP 33 nec 125 t2

Abstract: skiip 613 gb 123 ct RBS 6302 ericsson SKIIP 513 gb 173 ct THERMISTOR ml TDK 150M pioneer PAL 010a Project Report of smoke alarm using IC 555 doc SKiip 83 EC 125 T1 ericsson RBS 6000 series INSTALLATION MANUAL Ericsson Installation guide for RBS 6302
Contextual Info: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

or gate thruth table

Contextual Info: M54HC113 M74HC113 Æ 7 SCS-THOM SON ^ 7 # R if lQ ^ Q i[ L [ l( g ir [S @ M D ( g i DUAL J-K FLIP FLOP WITH PRESET • HIGH SPEED fMAX= 64 MHz (Typ.) at V c c = 5 V LOW POWER DISSIPATION ICC = 2 at TA = 25° C ■ HIGH NOISE IMMUNITY VniH = V n il= 28% VCc (MIN.)