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N74S113N Datasheets (3)

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Signetics

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
N74S113N		Signetics	Dual J-K Edge-Triggered Flip-Flop	Scan	PDF	128.51KB	5
N74S113N		Signetics	Dual J-K Edge Triggered Flip-Flop	Scan	PDF	133.69KB	5
N74S113N		Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF	917.21KB	27

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Rochester Electronics LLC SN74S113N 74S113 - Dual J-K Negative Edge-Triggered Flip Flops with Preset
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	SN74S113N		4,586		1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74S113NP1 J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74S113NP1		9,257			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74S113NP3 J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74S113NP3		7,762			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74S113N3 J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74S113N3		6,783			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74S113N1 J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74S113N1		6,170			1 - 10 - 100 - 1000 - 10000 -	Get Quote

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N74S113N Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
D 8243 HC Abstract: SO3A 6164 ram rb1-e N74S00 ITT301 N74S04 B177 55604A CD 5888 Contextual Info: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith	OCR Scan	n74s00n 55376d n74s02n 55377b +16n74s03n 55378x n74s04n 55379r n74s05n 5380a d 8243 hc so3a 6164 ram rb1-e n74s00 itt301 n74s04 b177 55604a cd 5888	PDF
74LS113 Abstract: C0056 Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro nous S e t Sq input, w hen LOW , forces	OCR Scan	74ls113 1n916 1n3064 500ns +1c0056	PDF
74LS113 Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113 Contextual Info: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro	OCR Scan	74ls113 tr113 1n916 1n3064 +6500ns 74ls 74s113 n74ls113n n74s113n s113	PDF
B147 Abstract: B237 ITT301 N74S00 6164 ram memory 74S189 CD 5888 md 8243 N74S00N N74S02N Contextual Info: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith	OCR Scan	n74s00n 55376d n74s02n 55377b +14n74s03n 55378x n74s04n 55379r n74s05n 5380a b147 b237 itt301 n74s00 6164 ram memory 74s189 cd 5888 md 8243	PDF
74LS113 Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro nous Set S d input, w hen LOW, forces	OCR Scan	74ls113 1n916 1n3064 500ns	PDF
74LS113 Abstract: S113 equivalent Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro nous Set Su input, when LOW, forces	OCR Scan	74ls113 wf08450s 1n916 1n3064 +2500ns s113 equivalent	PDF
THERMISTORS nsp 037 Abstract: Thyristor TAG 9118 ICA 0726 0148 Transformer a1273 y k transistor AM97C11CN transistor SK A1104 PM7A2Q B8708 bzy79 yh 5032 Contextual Info: INDEX OF COMPONENTS A Section/Page No. A.C. Adaptor. Adaptor Kits BNC e tc . Adhesive Tapes. Adhesives, Various. Aerosols.	OCR Scan	200x300x360m thermistors nsp 037 thyristor tag 9118 ica 0726 0148 transformer +7a1273 y k transistor am97c11cn transistor sk a1104 pm7a2q b8708 bzy79 yh 5032	PDF
ttl nand gate Abstract: B237 CD 5888 N74S04 transistor b143 e.s N74S00 ITT301 74s200 N74S00N N74S02N Contextual Info: Signetics Integrated Circuits Schottky TTL Schottky TTL 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith	OCR Scan	n74s00n 55376d n74s02n 55377b +14n74s03n 55378x n74s04n 55379r n74s05n 5380a ttl nand gate b237 cd 5888 n74s04 transistor b143 e.s n74s00 itt301 74s200	PDF
diode LT 42 PR 3002 Abstract: 5603A intersil b34 DIODE schottky ic 74s201 mmi 6331 74s188 74S474 74S288 FU 3024 82s141 Contextual Info: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith	OCR Scan	n74s00n 55376d n74s02n 55377b +16n74s03n 55378x n74s04n 55379r n74s05n 5380a diode lt 42 pr 3002 5603a intersil b34 diode schottky ic 74s201 mmi 6331 74s188 74s474 74s288 fu 3024 82s141	PDF
transistor cross reference Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466 Contextual Info: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC	OCR Scan	transistor cross reference mpt3n40 westinghouse scr handbook lt 8224 zener diode +6sje389 n9602n npn transistor rca 467 tfk 7 segment displays put 2n6027 delco 466	PDF
transistor C3866 Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246 Contextual Info: BID CΚΤ DOLLY L IST L OGO LIST SA F E TY & RELIA ΒL TY ΤΕΚ PIN SYSTE M DIGITA L IC's MEMORIES, MOS CMOS .EC L , TT L MICR OP R OC E SSOR SPE CIA L FUN CTION IC's DIGITAL l LINE AR K ARR AYS LIN E A R IC's (PUR CH ) ΤΕΚ-MADE IC's IC's INDEX (COL ORE D PGS)	Original	transistor c3866 zener ph sec e13009 ups circuit schematic diagram 1000w +6e13007 2 e13007 c3866 power transistor texas ttl 74l505 transistor c3246	PDF
74LS113 Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113 Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a d u a l J -K n e g a tive edg e trig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t and C lo c k inp u ts. T h e a s y n c h ro	OCR Scan	74ls113 1n916 1n3064 500ns +574ls 74s113 n74ls113n n74s113n s113	PDF
74LS113 Contextual Info: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro nous S et Sp input, when LO W , forces	OCR Scan	74ls113 500ns 1n916 1n3064	PDF