B2LHFL27 Search Results

M74LS174P

Abstract: 20-PIN 251C
Contextual Info: MITSUBISHI LSTTLs M 74LS174P LOPS W IT H RESET HEX D -l DESCRIPTION The M 7 4L S 17 4P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 6 D -type edge-triggered flip -flo p circuits w ith common clock input T and direct reset input R D as well

M74LS240P

Abstract: la 7610 d 667c
Contextual Info: M ITSUBISHI L S T T L s M 74LS240P OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS INVERTED DESCRIPTION The M 74LS240P PIN CONFIGURATION (TOP VIEW) is a s e m ic o n d u c to r integrated c irc u it a n d c o m m o n o u tp u t c o n tro l in p u t f o r all 4 d iscrete c irc u its .

semiconductor w5c

Abstract: 20-PIN 251C M74LS395AP
Contextual Info: MITSUBISHI LSTTLs M74LS395AP 4 -B IT CASCADABLE S H IFT REG ISTER W IT H 3-S TA TE O UTPUT DESCRIPTION T h e M 7 4 L S 3 9 5 A P is a s em ico n d u c to r in teg ra te d c irc u it PIN CONFIGURATION TOP VIEW co n ta in in g a 3-state o u tp u t 4 -b it s e rial/p a ralle l in p u t-s e ria l/

20-PIN

Abstract: 50J2 M74LS386P
Contextual Info: MITSUBISHI LSTTLs M74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

M74LS640-1P

Abstract: 20P4 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS640-1P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74L S 64 0-1P is a semiconductor integrated circuit containing 8 bus transmitters/receivers w ith inverted ou t­ puts. DATA

BCD-TO-7-SEGMENT DECODER

Abstract: m74ls248p M74LS247P M74LS48P m74ls48 M74LS47P
Contextual Info: MITSUBISHI LSTTLs M74LS248P B C D -TO -7 -SEGM ENT D EC O D ER /D R IVER A C TIV E -H IG H O U TP U T DESCRIPTION The M 7 4L S 24 8P is a semiconductor integrated circuit pro­ vided w ith a BCD-to-7-segment decoder/driver function and 2kohm (typ ) pull-up resistor outputs.

M74LS138P

Abstract: M74LS137P 20-PIN demultiplexer containing latch 1329T
Contextual Info: MITSUBISHI LSTTLs M74LS137P 3-LINE-TO -8-LINE DECODER/DEMULTIPLEXER W ITH ADDRESS LATCH DESCRIPTION The M 7 4L S 13 7P is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW taining a 3-line-to-8-line decoder/m ultiplexer function w ith address latch.

20-PIN

Abstract: M74LS670P
Contextual Info: MITSUBISHI LSTTLs M74LS670P 4 -B Y -4 REGISTER FILE W ITH 3-STATE OUTPUTS DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS670P is a semiconductor integrated circuit containing a 4 word x 4 bit register file circuit with 3-state outputs. i Di — [7 16] V cc

20-PIN

Abstract: M74LS37P
Contextual Info: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES

M74LS540P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS540P OCTAL BUFFER/LINE DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74L S 54 0P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit _ O UTPUT containing 1 block o f buffer w ith 3-state inverted output

M74LS684P

Abstract: 8BIT MAGNITUDE COMPARATOR M74LS682P M74LS683P M74LS685P M74LS688P M74LS689P
Contextual Info: MITSUBISHI LSTTLs ^ M 74LS684P S -B IT M A G N ITU DE COMPARATOR DESCRIPTION T h e M 7 4 L S 6 8 4 P is a s em ico n d u c to r in teg rated c irc u it c o n ­ PIN CONFIGURATION TOP VIEW ta in in g tw o 8 -b it w o rd s c o m p a ra to r fu n ctio n s .

M74LS247P

Abstract: 7 segment 4" LT display M74LS47P 4 digits 7-segment led display display 7 segment smd 4 digits 7-segment display cl BCD-TO-7-SEGMENT DECODER 4 digits 7-segment led display cl BCD-TO-7-SEGMENT 7 segment 4 LT display
Contextual Info: MITSUBISHI LSTTLs M74LS247P B C D -TO -7-S EG M E N T D E C O D E R /D R IV E R A C T IV E -L O W O U TP U T DESCRIPTION The M74LS247P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) provided with BCD-to-7-segment decoder/driver function

M74LS377P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 7 4 L S 3 7 7 P OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP W ITH ENABLE DESCRIPTION The M 7 4L S 37 7P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 8 D -type positive edge-triggered flip -flo p circuits

20-PIN

Abstract: M74LS298P M74LS298
Contextual Info: MITSUBISHI LS TT Ls M 74LS298P QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE DESCRIPTION The M74LS298P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW which containing fo u r 2-line to 1-line m ultiplexers provided w ith a tem porary storage circu it w ith common selection

M74LS166AP

Abstract: 50J2 M74LS166P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS166AP 8 -B IT SH IFT REGISTER DESCRIPTION The M 7 4L S 16 6A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8-bit serial/parallel input — serial ou tp u t shift register function. S E R IA L DATA

M74LS92P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS92P DIVIDE-BY-TW ELVE COUNTER DESCRIPTION The M74LS92P is a semiconductor integrated circuit containing an asynchronous divide-by-twelve counter func­ tion w ith direct reset inputs. FEATURES • • • • Direct reset input provided

m74ls194ap

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS194AP 4 -B IT B ID IR E C TIO N A L U N IV ER SA L S H IF T REG ISTER W IT H RESET DESCRIPTION The M 7 4L S 19 4A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW w ith a 4-b it bidirectional serial/parallel input-serial/parallel

M74LS126AP

Abstract: 20-PIN 12kf
Contextual Info: MITSUBISHI LSTTLs M 74LS126AP Q U AD R U PLE BU S BU FFER G A TE WITH 3-STA TE O UTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS126AP is a semiconductor integrated circuit containing 4 buffers w ith 3-state outputs and is provided w ith an o u tp u t control in p u t OC which is independent fo r

M74LS38P

Abstract: mitsubishi air conditioning 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS38P Q U AD R UPLE 2 -IN P U T P O S IT IV E NAND BUFFER W IT H OPEN COLLECTOR OUTPU T DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS38P is a semiconductor integrated circu it containing fo u r 2-input positive N AN D and negative NOR

M74LS12P

Abstract: 74LS12P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 7 4 LS1 2 P T R IP L E 3-INPUT P O SITIV E NAND GATE WITH OPEN CO LLECTO R OUTPUT DESCRIPTION The M74LS12P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing three triple-input positive-logic NAND gates with open collector outputs, usable as negative-logic NOR

Contextual Info: MITSUBISHI LSTTLs M74LS367AP H EX BUS D R IVER S W IT H 3 -S T A T E O UTPU TS DESCRIPTION The M 7 4L S 36 7A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW constaining 6 buffers w ith 3-state ou tp ut and is provided w ith ou tp u t control

74LS86p

Abstract: M74LS86P
Contextual Info: M IT S U B IS H I LSTTLs M 74LS86P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATES DESCRIPTION The M 7 4L S 86 P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing 4 dual-input exclusive-OR gates. FEATURES • , High breakdown input voltage (V | i 1 5 V )

Contextual Info: MITSUBISHI LS T T Ls M74LS353P DUAL 4-LIN E TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74LS 353P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing tw o 4-line to 1-line data selector/m ultiplexer

M74LS123P

Abstract: 74LS4 m74ls123
Contextual Info: MITSUBISHI LSTTLs M 74LS423P DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M74LS423P is a semiconductor integrated c irc u it containing tw o retriggerable monostable m u ltivib ra to r cir­ cuits w ith direct reset inputs.