74LS4 Search Results

54LS466

Abstract: 74LS467 74LS465 74LS468 74ls46 81LS98 74ls466
Contextual Info: SN54LS465 THRU SN54LS468, 74LS465 THRU 74LS468 OC TAL BU FFERS W ITH 3 S T A T E OUTPUTS D 2 6 3 1 , JA N U A R Y 1981 - SN 54LS465 AND SN 54LS466 . . . J PACKAGE SN 74LS465 AND SN 74LS466 . . . DW OR N PACKAGE TOP VIEW! G1 A1 • 3-State Outputs Rated at lo L o f 12 m A and

74LS42

Abstract: PIN 74LS42 data sheet 74ls42 LS42 sn5474ls42
Contextual Info: SN54/74LS42 ONE-OF-TEN DECODER The LSTTL / MSI SN54 / 74LS42 is a Multipurpose Decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. The LS42 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

54LS423

Abstract: 74LS422 SM74LS42 54LS422
Contextual Info: SN54LS422, SN54LS423, 74LS422, 74LS423 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS D2536, JANUARY 1980 - REVISED MARCH 1988 Will Not Trigger from Clear SN 54LS422 . . J OR W PACKAGE SN 74LS422 . . . D OR N PACKAGE D-C Triggered from Active-High or ActiveLow Gated Logic Inputs

Contextual Info: • BCD-tO’Seven Segment Decoder/Driver with Open collector outputs IP IN ARRANGEMENT The H D 74LS49 features active-high outputs for driving lamp buffer. This circuit incorporates d direct blanking input. Segment identification and resultant displays are shown below.

74LS40

Abstract: 74LS40D IC 7440
Contextual Info: 40 CO NNECTIO N DIAGRAMS PINOUT A 54/7440 0 '° / l^ H / 7 4 H 4 0 o n o ^ 'v ^ 4 S / 7 4 S4 0 o / f c L/'l ^54LS/74LS40 C'Oi DUAL 4-INPUT NAND BUFFER ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE Vcc = +5.0 V ±5%, T a = 0 °C to +70° C

Contextual Info: SN5442A, SN54LS42, SN74442A, 74LS42 4 LINE BCD TO 10 LINE DECIMAL DECODERS M AR C H 1 9 7 4 -R E V IS E D MARCH All Outputs Are High for Invalid Input Conditions S N 5442A , SNS4LS42 . J OR W PACKAGE SN 7442A . . . N PACKAGE SN 74LS42 . . . D OR N PACKAGE

SN54LS440

Abstract: SN54LS442 SN54LS444 SN74LS440 SN74LS442 SN74LS444
Contextual Info: SN 54LS440 THRU S N 54LS 442, SN54LS444 74LS440 THRU S N 74LS 442, SN 74LS444 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS SDLS176 • 3 -W a y A s y n c h ro n o u s C o m m u n ic a tio n □ 2 4 2 5 , A U G U S T 1 9 7 9 -R E V IS E D M AR C H 1 9 8 8 S N 54L S ' . . . J PACKAGE

motorola 74ls47

Abstract: 74LS47 ttl 74ls47 74LS47 functions ttl 74ls47 7 segment LS 74LS47 of 74ls47 7-segment 74ls47 74LS47 pin configuration 74LS47 pin
Contextual Info: g MOTOROLA SN54/74LS47 BCD TO 7-SEGMENT DECODER/DRIVER The S N 54/74LS 47 are Low Power Schottky BCD to 7-Segment Decod­ er/D rivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving

74ls44

Abstract: 74LS445 1N3064 1N916 74LS N74LS445N
Contextual Info: Signetìcs 74LS445 Decoder/Driver BCD-To-Decimal Decoder/Driver Open Collector Product Specification Logic Products FEATURES • • • • 80mA output drive capability 7V output breakdown voltage See '45 for 30V output voltage See '42 for standard TTL outputs

74LS40

Abstract: truth table NOT gate 74 751A-02
Contextual Info: g MOTOROLA SN54/74LS40 DUAL 4-INPUT NAND BUFFER DUAL 4-INPUT NAND BUFFER Vcc ra ra ra ra ra it i LOW POWER SCHOTTKY m J SUFFIX CERAMIC CASE 632-08 LU LU LÜ LU LU LU üü GND J^pi n s u f f ix D SUFFIX s o ic , CASE 751A ORDERING INFORMATION SN54LSXXJ SN74LSXXN

PLD12

Abstract: 74LS429 N74LS429N PLD11 1N814 "FRC"
Contextual Info: 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in multiples of 2

M74LS123P

Abstract: 74LS4 m74ls123
Contextual Info: MITSUBISHI LSTTLs M 74LS423P DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW 74LS423P is a semiconductor integrated c irc u it containing tw o retriggerable monostable m u ltivib ra to r cir­ cuits w ith direct reset inputs.

74LS40

Contextual Info: g M O TO R O LA SN54/74LS40 D U A L 4-INPUT N A N D BUFFER unii H L±J LsJ LU H LOW POWER SCHOTTKY J Suffix — Casa 632-08 {Ceramic) N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES SYM B O L MIN TYP MAX UNIT Vcc Supply Voltage PARAMETER

Contextual Info: M MOTOROLA SN54/74LS490 DUAL DECADE COUNTER The S N 54/74LS 490 contains a pair of high-speed 4-stage ripple counters. Each half of the S N 54/74LS 490 has individual Clock, Master Reset and Mas­ ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.

74ls491

Contextual Info: July 1989 DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET overrides LOAD, COUNT and HOLD. LOAD overrides COUNT.

IC TTL 7440

Abstract: IC 7440 IC 74LS40
Contextual Info: 7440, LS40, S40 Signetics Buffers Dual Four-Input NAND Buffer Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7440 11ns 11mA 74LS40 12ns 1.8mA 74S40 6ns 18mA ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to +70°C

Contextual Info: LS TTL DN74LS Series 74LS490 KH4U4qo 74LS490 Dual 4 -bit Decade Counters • D escrip tio n DN 74LS490 contains two asynchronous decade counter circuits with direct coupled reset input and nine direct-coupled set inputs. P -2 ■ Features • Two circuits corresponding to LS90 and L S290 for high

DM74LS491N

Contextual Info: LS491 S National Semiconductor DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

74LS429

Contextual Info: 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in multiples of 2

Contextual Info: SANYO SEMICONDUCTOR CORP 1S E D I 7 en 7 G 7 b OGOSbMñ T-t>7 -2.l-s-7 mU%ffÊÊÊÉ# C7 4 HC42 3006B C M O S H igh-Speed Standard Logic LC 74H C Series BCD to Decimal Decoder S 2 0 2 5A Features • The LC74HC42 is a BCD-to-decimal decoder. • Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL 74LS42 w ith the

74ls490

Contextual Info: 74LS490 Signetics Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES TYPE • T w o B C D d e c a d e c o u n te rs • A s y n c h ro n o u s M a s te r S e t s e t-to -9 • A s y n c h ro n o u s M a s te r R e s e t

IC 74LS42 N

Abstract: 3035AM
Contextual Info: SANYO SEMICONDUCTOR CORP LC74HC42M 10 CMOS High-Speed Standard Logic LC74HC Series 3035a * " — -' BCD to Decimal Decoder ^ 2098A ’ ‘ Features . • The LC74HC42M decodes a B C D address to one-of-ten active-low outputs. • Uses C M O S silicon gate process technology to achieve operating speeds similar to LS-TTL 74LS42 with the

54LS42J

Abstract: cn7a
Contextual Info: SN5442A, SN54LS42, S N 74 4 4 2 A , S N 74LS 42 4-LINE BCD TO 10-LINE DEC IM AL DECODERS M A R C H 1 9 7 4 - R E V IS E D M A R C H • • • All Outputs Are High for Invalid Input Conditions S N 5 44 2A , S N 54LS42 S N 7 4 4 2 A . . . N P AC K A G E SN 74LS42

M74LS42P

Abstract: 74LS42P mitsubishi DECODER 20-PIN
Contextual Info: DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS42P is a semiconductor integrated circuit provided with a BCD-to-decim al decoder function. FEATURES ÿô — • A ll outputs set high with reactive input • Usable as a 3-bit binary /octal decoder - [7