74LS SERIES Search Results

lm294oct

Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Contextual Info: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12

octal Bilateral Switches

Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
Contextual Info: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters

Contextual Info: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary

Contextual Info: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

74ALS192

Abstract: IC 74LS192 LS192 ALS192 MODULO-16 DV74LS192 DV74LS192-93 LS193
Contextual Info: AVG Semiconductors DDT Technical Data The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The out­

ls190

Abstract: 30132 10116
Contextual Info: 190,191 AVG Semiconductors DDT Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are

74Ls79

Contextual Info: M MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The S N 54/74LS 795 thru S N 54/74LS 798 device types provide a second source for the 7 1 /8 1 LS95 thru 71 /81LS 98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex

74ls795

Abstract: 74LS796 74ls797
Contextual Info: M MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The S N 54/74LS 795 thru S N 54/74LS 798 device types provide a second source for the 71 /8 1 LS95 thru 7 1 /8 1 LS98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex

Contextual Info: M MOTOROLA SN54/74LS623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUT The SN 54/74LS 623 series is an octal bus transceiver designed for asynchronous two-way com munication between data buses. Control function implementation allows maximum timing flexibility. Enable inputs may be used

LDT1

Contextual Info: Plastic Fiber Optical Data Link LD Series •Features 1. Low pulse width distortion. 2. This is a TTL and CMOS compatible interface. Direct coupling permitted to 74LS and 74HC 3. Full-lock connectors in which the optical connectors use a lock lever in the

DN74LS245

Contextual Info: DN74LS245 LS TTL 74LS Series DN74LS245 ro 74LS^4-S' Octal Bus Transceivers with 3 -state Outputs P-3 • Description DN74LS245 contains eight bus transmitter/receiver circuits with non-inverted outputs. ■ Features • Bidirectional transfer or separation capability for two 8-bit

74ls series logic family

Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
Contextual Info: INTEGRAL KOREA Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4

cmos logic 4000 series

Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
Contextual Info: z Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4 HD14 MC14 TC4

74SC244

Contextual Info: f+ f MITEL Technical Di MDB4SCB40, MD54SCB41, MD54SC540, MD54SC541 MD74SCB40, MD74BCS41. M D74SC540, MD74SC541 ISO-CMOS, 3-State Octal Buffers/Line Drivers MDB4SCB44 MD74SC844 Features Ordering Information • E quivalent to 54/74LS’ series • Low pow er ISO-CMOS te ch n o lo g y

74LS183

Abstract: 74LS275 74LS97 74LS04 74LS00 74ls series 74LS356 74LS93 74LS396 74LS55
Contextual Info: CM O S/BiCM O S Gate Array • LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries LZ93/LZ95/LZ96/LZ97 Series Model No. Model No. Model No. Model No. Model No. Model No. Model No. 74LS00 74LS51 74LS107 74LS158 74LS193 74LS261 74LS364 74LS02 74LS54

SHARP LZ93

Abstract: 74ls series gate
Contextual Info: CM OS Gate Array LZ96 Series LZ96 Series • CMOS Gate Array ■ Description 1. CMOS process 2. Number of gates : 300, 650, 1170. 2000, and 4000 3. Internal gate delay 9.5ns/gate 1.5V operating voltage 4. Macro cell : 95cells 74LS cell : 126cells 5. I/O level : CMOS level

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P

Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.

MD154

Abstract: 74SC541A MD5408 LM054 74SC244 DJ01
Contextual Info: ISO-CMOS, 3 -S ta te Octal Buffers/Line Drivers M IT E L T e c h n ic a l D a t a MD54SCB40, MD548C241, MD548C540, MD548C541 MD74SCS40, MD74SCS41, MD74SC54Q, MD74SC541 MD54SCE44 OCT '8 2 MD74SCS44 Features Ordering Information • Equivalent to 54/74LS’ series

1S2074

Abstract: 74LS HD74LS166A HD74LS166AP PRDP0016AE-B hd74ls166
Contextual Info: HD74LS166A 8-bit Shift Register REJ03D0450-0400 Rev.4.00 May 10, 2006 The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift

Am2913

Contextual Info: Am2913 Am 2913 Priority Interrupt Expander DISTINCTIVE CHARACTERISTICS • • • Similar in function to Am54LS/74LS/25LS148/2513 Gated three-state output Advanced Low-Power Schottky processing Encodes eight lines to three-line binary Expands use of Am2914

74SC244

Contextual Info: O f f M I T E ISO-CMOS, 3-State Octal Buffers/Line Drivers L T e c h n ic a l D e MD84SC840, MD548CB41, MD548C540, M0548C541 MD74SCS40, MD743C241, MD74SC540, MD74SC541 MDB48CE44 OCT '8 2 MD74SCS44 Features Ordering Information • Equivalent to 54/74LS’ series

G74SC139P

Abstract: G74SC138 74LS series logic gates 3 input or gate 74LS G74SC137D G74SC137P G74SC138D G74SC138P G74SC139D
Contextual Info: G74SC137 G74SC138 G74SC139 Microcircuits CM OS Octal Decoders/Demultiplexers Feature* General Description • Equivalent to 74LS series This family of C M O S decoders/demultiplexers is designed for use in high speed memory and peripheral address decod­ ing systems. The G74SC138 decodes three binary inputs AO,

DN74LS290

Abstract: QD32
Contextual Info: LS TTL 74LS Series DN74LS290 DN74LS290 N>74LSÌ.<ÌO Decade Counters • Description P-1 D N 74LS290 is an asynchronous decade counter w ith a directcoupled reset in p u t and nine direct-coupled set inputs. ■ Features • • • • • Direct-coupled reset input