SN74ACT Search Results

CT 2048

Abstract: D8228
Contextual Info: SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L 2048 x 9,4096 x 9,8192 x 9,16384 x9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 Reads and Writes Can Be Asynchronous or Coincident Organization: - SN74ACT7203L - 2048 x 9

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: SN74ACT2235 1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148E - DECEMBER 1990 - REVISED APRIL 1998 • Independent Asynchronous Inputs and Outputs • Access Times of 25 ns With a 50-pF Load • Data Rates up to 50 MHz • Low-Power Advanced CMOS Technology

SN74ACTOO

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C A S 5 2 3 A -AU G U S T 199S - R E V IS E D MAY 1996 Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS 1-ixm Process Package Options Include Plastic Small-Outllne (D), Shrink Small-Outllne

Contextual Info: SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50 512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY D3101. MARCH 1988 • Asynchronous Operation S N 74A C T72 01A . . . N PACKAGE TOP VIEW • Lower Power Consumption Active . . . 400 mW Power Down . . . 3 mW

Contextual Info: SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS550A – NOVEMBER 1995 – REVISED 1996 D D D SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Drive Bus Lines

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT14, SN74ACT14 HEX SCHMITT-TRIGGER INVERTER SCAS557D – DECEMBER 1995 – REVISED MARCH 1998 D D D Inputs Are TTL-Voltage Compatible EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516B – JUNE 1995 – REVISED MAY 1996 D SN54ACT241 . . . J OR W PACKAGE SN74ACT241 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 D D D D D D D D D D DL PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: SN74ACT08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS779 − SEPTEMBER 2004 D Controlled Baseline D D D D D Inputs Accept Voltages to 5.5 V D Max tpd of 10 ns at 5 V D Inputs Are TTL-Voltage Compatible − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74ACT2158, SN74ACT2159 8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs D 3 2 8 1 , M A Y 1 9 9 0 R E V IS E D J U N E 1990 Fast Address to MATCH Delay 22 ns Max FN PACKAGE TOP VIEW 8K x 10 Internal Static RAM ISCI 5 Ä • Word Reset Function for Single Entry

SN74ACT244MNSREP

Contextual Info: SN74ACT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS724B – OCTOBER 2003 – REVISED MARCH 2006 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of up to

SN54ACT245

Abstract: SN74ACT245 SN74ACT245DBR SN74ACT245DW SN74ACT245DWR SN74ACT245N SN74ACT245NSR SN74ACT245PWR SNJ54ACT245J SN74ACT245PWLE
Contextual Info: SN54ACT245, SN74ACT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS452E – SEPTEMBER 1994 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8 ns at 5 V Inputs Are TTL-Voltage Compatible SN54ACT245 . . . J OR W PACKAGE

AD574 application note

Abstract: ACT574 SN54ACT574 SN74ACT574 SN74ACT574DBR SN74ACT574DW SN74ACT574DWR SN74ACT574N SN74ACT574NSR SN74ACT574PWR
Contextual Info: SN54ACT574, SN74ACT574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS537D − OCTOBER 1995 − REVISED NOVEMBER 2002 SN54ACT574 . . . J OR W PACKAGE SN74ACT574 . . . DB, DW, N, NS, OR PW PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V

A115-A

Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels D D D D D D D D DW OR NS PACKAGE TOP VIEW on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation

Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS531C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 10.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT11 . . . FK PACKAGE

Contextual Info: SN74ACT04ĆEP HEX INVERTER SCAS781 − OCTOBER 2004 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification Qualification Pedigree† 4.5-V to 5.5-V VCC Operation

Contextual Info: SN54ACT74, SN74ACT74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 10.5 ns at 5 V D Inputs Are TTL-Voltage Compatible

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516C – JUNE 1995 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8.5 ns at 5 V Inputs Are TTL Compatible SN54ACT241 . . . FK PACKAGE

Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

Contextual Info: SN54ACT11, SN74ACT11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS531C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 10.5 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT11 . . . FK PACKAGE

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 D D D D D Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be Synchronized to Independent System