SCAA035B Search Results

AHC08

Abstract: scaa035b LOW POWER CMOS LOGIC FAMILIES AHC14 AHC374 SCAA035
Contextual Info: CMOS Power Consumption and Cpd Calculation SCAA035B June 1997 1 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

Contextual Info: SN74LVCH162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545G – OCTOBER 1995 – REVISED JUNE 1999 D D D D D D D D D D D DL OR DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process

Contextual Info: SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS303H – JANUARY 1993 – REVISED AUGUST 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54HC374, SN74HC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS141C – DECEMBER 1982 – REVISED JULY 1998 D D D D SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Eight D-Type Flip-Flops in a Single Package

SCBA004C

Abstract: scaa035b
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS287 This data sheet is applicable to the CD54/74AC240, CD54ACT240, CD54AC241, and CD54/74ACT241. The CD74AC241 was not acquired from Harris Semiconductor. See SCHS244 for information on the CD74ACT240, CD74AC244, and CD74ACT244.

SNJ54HC373FK

Contextual Info: SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B – DECEMBER 1982 – REVISED MAY 1997 D D D D Eight High-Current Latches in a Single Package High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads Full Parallel Access for Loading

Contextual Info: SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS554A – NOVEMBER 1995 – REVISED MAY 1996 D D D SN54AC534 . . . J OR W PACKAGE SN74AC534 . . . DB, DW, N, OR PW PACKAGE TOP VIEW 3-State Inverting Outputs Drive Bus Lines

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148C – DECEMBER 1982 – REVISED JANUARY 1998 D D SN54HC574 . . . J OR W PACKAGE SN74HC574 . . . DW, N, OR PW PACKAGE TOP VIEW High-Current 3-State Noninverting Outputs

Contextual Info: SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS295J – JANUARY 1993 – REVISED JUNE 1998 D D D D D D description SN54LVC373A . . . J OR W PACKAGE SN74LVC373A . . . DB, DW, OR PW PACKAGE TOP VIEW OE 1Q 1D 2D 2Q 3Q 3D

Contextual Info: SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR SCLS122B – DECEMBER 1982 – REVISED MAY 1997 D D D D D Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54HCT245, SN74HCT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS020C – MARCH 1984 – REVISED MAY 1997 D D D SN54HCT245 . . . J OR W PACKAGE SN74HCT245 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus

Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000 D D SN54HCT240 . . . J OR W PACKAGE SN74HCT240 . . . DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

pinout diagram of 4049

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205B High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised May 2000 Features

SN54AC04

Contextual Info: SN54AC04, SN74AC04 HEX INVERTERS SCAS519C – JULY 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54HC08, SN74HC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS081B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC08 . . . J OR W PACKAGE SN74HC08 . . . D, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W)

Contextual Info: SN54HC393, SN74HC393 DUAL 4-BIT BINARY COUNTERS SCLS143B – DECEMBER 1982 – REVISED MAY 1997 D D D D Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by Reducing Counter Package

Contextual Info: SN54HCT257, SN74HCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCLS072B – NOVEMBER 1988 – REVISED MAY 1997 D D D D D SN54HCT257 . . . J PACKAGE SN74HCT257 . . . N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS295J – JANUARY 1993 – REVISED JUNE 1998 D D D D D D description SN54LVC373A . . . J OR W PACKAGE SN74LVC373A . . . DB, DW, OR PW PACKAGE TOP VIEW OE 1Q 1D 2D 2Q 3Q 3D

Contextual Info: [ /Title CD74 HC137 , CD74 HCT13 7, CD74 HC237 , CD74 HCT23 7 /Subject (High Speed CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237 Data sheet acquired from Harris Semiconductor SCHS146A March 1998 - Revised May 2000 High Speed CMOS Logic, 3-to-8 Line Decoder