SN74ALVC125 Search Results

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

SN74ALVC125

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SC E S 110D - JULY 1997 - R EVISED D ECE M BE R 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

A115-A

Abstract: SN74ALVC125 SN74ALVC125D SN74ALVC125DR SN74ALVC125NSR VA125
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

Contextual Info: Contents Page ALVC Gates/Octals SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244 SN74ALVCH244 SN74ALVC245 SN74ALVCH245 SN74ALVCH373 SN74ALVCH374 2–2 Quadruple 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

va125

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D VA125 VA-125
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D VA-125
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES110F − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

VA-125

Abstract: A115-A C101 SN74ALVC125 SN74ALVC125D
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

C101

Abstract: SN74ALVC125 SN74ALVC125D A115-A
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D EPIC Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

SN74ALVC125NSR

Abstract: A115-A SN74ALVC125 SN74ALVC125D SN74ALVC125DR
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

A115-A

Abstract: C101 SN74ALVC125 SN74ALVC125D
Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates from 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

ATMEL 234

Abstract: how to derive sim 900 ARM926EJ-S AT91SAM ISO7816
Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer

TTL 74-series IC LIST

Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
Contextual Info: 04/18/07 Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi PO49FCT3802A 1GHz 1 to 5 PO49FCT3803B 700MHz 1 to 7 PO49FCT3804 800MHz 2X1 to 4 PO49FCT3805B 800MHz 2X1 to 5 PO49FCT3806 750MHz 2X1 to 5 PO49FCT3807B

ARM7TDMI System Peripherals

Abstract: program key lock ic 4013 154WA SAM7SE512 at91sam7sexx
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support

6242E

Abstract: 4583 dual schmitt trigger 6242b la 4508 ic pin diagram R1100D121C AT91Bootstrap CS 5609 ARM926EJ-S ISO7816 5609 dec
Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer

Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer