74LS 10 N Search Results

LS748

Abstract: 74LS147 74LS148 74lS748
Contextual Info: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order

Contextual Info: GD54/74HC42, GD54/74HCT42 1-QF-10 DECODER General Description These devices are identical in pinout to the 54 /74LS 42. Data on the 4 input pins select one of the 10 outputs corresponding to the value of the BCD number on the inputs. An output will go low

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51
Contextual Info: FAIRCHILD DIGITAL TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Item 9000 Series 8 ns/10 mW (Cont'd) Function’11 SSI FUNCTIONS 5 't/I

74ls gate symbols

Abstract: 74LS series logic gate symbols 74LS series logic gates 74LS logic gates oc 44 74LS TTL series 74LS D-32 buffer 74ls series logic gates 74LS AND GATE
Contextual Info: FAIRCHILD DIGITAL T T L Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram<2 Item ~c g o c 3 li. Low Power Schottky 54LS/74LS 5 ns/2 mW Cont’d) 9000 Series 8 ns/10 mW SSI FUNCTIONS

74LS08 Quad 2-Input AND Gates

Abstract: TTL 74s32 TTL 7408 or 2 input 74Ls32 74LS11 and 74LS32 74ls32 quad 2-input OR gates 54LS TTL 7421 74LS 3-input NOR 74LS11
Contextual Info: FAIRCHILD DIGITAL TTL High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2’ E £ Std. TTL 54/74 10 ns/10 mW ~c o o c S U. Low Power Schottky 54LS/74LS 5 ns/2 mW Cont’d 9000 Series 8 ns/10 mW SSI FUNCTIONS 5

Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.

Z427

Abstract: FL 9014 TTL 7409 TTL 7486 74LS32 74ls86 TTL 74s32 74LS08 74LS11 74LS02
Contextual Info: FAIRCHILD DIGITAL TTL SSI FUNCTIONS Cont’d X to x n agic/Conne Diagram igh Speed 54H/74H ns/22 mW O IO U) —1 ligh Speed Schottky 54S/74S ns/19 mW CO Std. TTL 54/74 1 ns/10 mW E a> Dw Power Schottky ILS/74LS ns/2 mW ~'c o u c 3 U. 9000 Series ns/10 mW

shiftregisters

Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock

7402PC

Abstract: 74LS02 pinout LS 7402 74LS02PC pinout 7402 74LS02 7402P 7402 DIP 74S02PC 5402DM
Contextual Info: 02 C O N NECTIO N DIAGRAMS PINOUT A "54/7402 C / / r r/ 9 ^ 4 S /7 4 S 0 2 ¿7 / / / ÛS ^S 4LS /74LS 02 w e 3 QUAD 2-INPUT NOR GATE ORDERING CODE: See S ection 9 PKGS PIN COM M ERCIAL GRADE M ILITARY GRADE OUT V cc = +5.0 V ±5%, Ta = 0 °C to +70° C V cc = +5.0 V ± 10%,

ic 74HC138

Abstract: 74HC138N 74hc138m 74HC138 MM74HC138M 74HC138A
Contextual Info: A I R C H S eptem ber 1983 I L D Revised February 1999 S E M IC O N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder's outputs can drive 10 low pow er Schottky TT L e quivalent loads, and are functionally and pin equiva­ lent to the 74LS 138. All inputs are protected from dam age

54LS42J

Abstract: cn7a
Contextual Info: SN5442A, SN54LS42, S N 74 4 4 2 A , S N 74LS 42 4-LINE BCD TO 10-LINE DEC IM AL DECODERS M A R C H 1 9 7 4 - R E V IS E D M A R C H • • • All Outputs Are High for Invalid Input Conditions S N 5 44 2A , S N 54LS42 S N 7 4 4 2 A . . . N P AC K A G E SN 74LS42

7 segment 14-pin

Abstract: 74LS249 LS249 LS49 54LS249DM 54LS249FM 74LS249DC 74LS249FC 74LS249PC
Contextual Info: 249 C O N N E C T IO N D IA G R A M P IN O U T A f 54LS /74LS 249 BC D T O 7 -S E G M E N T D EC O D ER W ith O p e n -C o lle c to r O utputs A, [T T i l V cc a2 [7 1?| f LT ( T b i/ b b ö T51 a RBI [T Ï 2I b a 3 (T TT| C [T 10] d GND [T ~9~| e ao D E S C R IP T IO N — T h e ’LS249 has a ctive H IG H o p e n -c o lle c to r o u tp u ts and is

rs flip-flop IC 7400

Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
Contextual Info: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper­ ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)

LM 7410

Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

IC 7438

Abstract: IC TTL 7438 IO 7438 74ls38 IC 74ls38 LS38 7438
Contextual Info: Signelics I 7438, LS38, S38 Buffers Quad Two-Input NAND Buffers Open Collectors Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7438 13ns 28mA 74LS38 19ns 3.5mA 74S38 6.5ns 33mA ORDERING CODE COMMERCIAL RANGE

74LS266 pin configuration

Abstract: TTL 74LS266 74ls Logic Family Specifications 74LS 74Ls signetics
Contextual Info: 74LS266 Signetics Gate Quad 2-Input Exclusive-NOR Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 18ns 8mA 74LS266 FUNCTION TABLE INPUTS ORDERING CODE OUTPUT A B Y L L H H L H L H H L

IC TTL 7440

Abstract: 74s40 IC 74LS40 IC 7440
Contextual Info: 7440, LS40, S40 Signelics Buffers Dual Four-Input NAND Buffer Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7440 11ns 11mA 74LS40 12ns 1.8mA 74S40 6ns 18mA ORDERING CODE COMMERCIAL RANGE VCc = 5V ±5% ; T a = O X to +70°C

74ls139 decoder pin configuration

Abstract: 74LS139 74LS139 pin configuration with S139 demultiplexer 74ls 74LS139 application 74LS139 equivalent 74ls139 pin diagram 74S139 74LS
Contextual Info: 74 LS1 3 9, S139 Decoders/Demultiplexers S ig n e t ic s Dual 1-of-4 Decoder/Demultiplexer Product Specification Logic Products FEATURES • • • • Demultiplexing capability Two independent 1-of-4 decoders Multifunction capability Replaces 9321 and 93L21 for

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

Contextual Info: 74LS620, LS623 Signetics Transceivers 'LS620 Inverting Octal Bus Transceiver 3-State 'LS623 Non-Inverting Octal Bus Transceiver (3-State) Product Specification Logic Products FEATURES • Octal bidirectional bus Interface • 3-State buffer outputs - LS620, inverting

ci 7492

Abstract: 7492 counter TTL 7492 7492 binary counter 7492 74LSS2 ci+7492
Contextual Info: 7492, LS92 Signetics Counters Divide-By-Twelve Counter Product Specification Logic Products DESCRIPTION The '92 is a 4-bit, ripple-type Divide-by12 Counter. The device consists of four master-slave flip-flops internally con­ nected to provide a divide-by-two sec­

7427 pin configuration

Abstract: TTL 7427 7427 TTL 7427 NOR propagation delay 74ls gate symbols logic gate 7427 NOR pin configuration of 7427 7427 SIGNETICS 74LS LS27
Contextual Info: Signetics I 7427, LS27 Gates Triple Three-Input NOR Gate Product Specification Logic Products TYPICAL SUPPLY CURRENT TOTAL TYPICAL PROPAGATION DELAY TYPE 7427 9ns 13mA 74LS27 10ns 2.7mA ORDERING CODE COMMERCIAL RANGE VCC = 5 V ± 5% ; T a = 0°C to + 7CTC

74ls82

Abstract: 74LS820 ls623 74LS623 LS620 1N3064 1N916 74LS 74LS620 N74LS620N
Contextual Info: 74LS620, LS623 Signetics Transceivers 'LS620 Inverting Octal Bus Transceiver 3-State 'LS623 Non-Inverting Octal Bus Transceiver (3-State) Product Specification Logic Products FEATURES • O c ta l b id ire c tio n a l bu s In te rfa c e • 3 -S ta te b u ffe r o u tp u ts