74LS09 Search Results

ALU IC 74181

Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn

Contextual Info: GD54/74LS09 QUADRUPLE 2-INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS Description Pin Configuration This d evice contains four ind epen den t 2-input AND gates. It performs the Boolean functions Y = A • B or Y = A + B in positive logic. T h e open-collector out­

74ls gate symbols

Abstract: 74LS09 equal 74LS09 function table 74LS09 74LS logic gates 74LS09 N 74LS09 ttl 1N3064 1N916 74LS
Contextual Info: SigneHcs I 74LS09 I Gates Logic Products I Quad Two-Input AND Gate Open Collector f l Product Specification • TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23 ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5 V ± 5% ; TA = 0°C to +70°C

Contextual Info: MITSUBISHI LSTTLs 74LS09P QUADRUPLE 2-IN P U T POSITIVE AND GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS09P c o n ta in in g 4 is a s e m ico n d u c to r d u a l-in p u t positive AND in teg rated c irc u it and negative O R gates w ith op en c o lle c to r o u tp u t.

74LS09PC

Contextual Info: 09 CONNECTION DIAGRAM PINOUT A v£4/7409 O''bV V V54S/74S09 '/54LS/74LS09 t?r0 / ' 2 QUAD 2-INPUT AND GATE With Open-Collector Output ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5,0 V ±10%,

74LS09 ttl truth table

Abstract: SN74LSXXD 751A-02 74LS09 ttl 74LS09 N 74 and or SN54LSXXJ SN74LSXXN high voltage 2 input and
Contextual Info: SN54/74LS09 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 * * * 1 2 8 * 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

Contextual Info: Signelics I 74LS09 I Gates I I Logic Products Quad Two-Input AND Gate Open Collector Product Specification I TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; T a = 0°C to +70°C

CI 74LS08

Abstract: 7432 TTL fairchild TTL 7421 74LS21 ttl 7432 TTL 74ls32 TTL 7409 TTL 7486 TTL 74ls86 TTL 7432 fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi

Contextual Info: GD54/74HC09, GD54/74HCT09 QUAD 2-INPUT AND GATES WITH OPEN-DRAIN OUTPUTS General Description These devices are identical in pinout to the 54/74LS09. They contain four independent 2-Input AND gates. The open-drain outputs require pull-up resistors to perform correctly. With suitable pull-up

74LS09 N

Contextual Info: Signelics | 74LS09 Gates Quad Two-Input AND Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5% ; T a = 0°C to +70°C

74LS09

Abstract: 74ls gate symbols 74LS09 ttl 1N3064 1N916 74LS N74LS09N 74LS gates 74ls signetics 74LS logic gates
Contextual Info: Signelics I 74LS09 I G ates • Quad Two-Input AND Gate Open Collector ■ Logic Products Product Specification H TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; T a = 0°C to +70°C

N7409F

Abstract: N7409N N74LS09F N74LS09N N74S09F N74S09N S5409F S54LS09F S54S09F
Contextual Info: 54/7409 54S/74S09 54LS/74LS09 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES ± 5%; T a = 0 "C to *70°C PACKAGES PIN C O N F. P lastic DIP Fig. A Fig. A N7409N • N74S09N 74LS09N C eram ic DIP

74LS09 ttl

Abstract: 751A-02 74LS09 ttl truth table
Contextual Info: SN54/74LS09 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 * * * 1 2 8 * 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74Ls signetics

Abstract: 74LS logic gates IC 74LS 74LS09 ttl ic ttl 74ls 74ls ic 74LS09 function table
Contextual Info: 74LS09 Signetics Gates Quad Two-Input AND Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V + 5%; T A = 0”C to +70°C

TTL 7486

Abstract: FL 9014 TTL 7421 ttl 7432 TTL 7411 TTL 7409 7486 TTL 7411 74LS86 74LS08
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi ly i r n

DN74LS09

Contextual Info: LS TTL DN74LS Series DN 74LS09 74LS09 DN 74L t y * Quad 2 - input P o s i t i v e A N D Gates with Open Co ll ec to r Outputs) H D escription P -1 D N 7 4 L S 0 9 c o n ta in s f o u r 2-in put positive is o la tio n A N D gate c ir cuits w it h o p e n c o ll e cto r o u tp u ts .

400EM

Abstract: 472EM cdb 400E CI 74151 CDB404E 4153E 7404 7408 7432 4121EM IC TTL 7460 446E
Contextual Info: JBIGITAl_ _ INTEGRATED IK* m m X.X.L. . L 5400 5402 5403 5404 5405 5406 5407 5408 5409 5410 5413 5416 5417 5420 5430 5432 5437 5438 5440 5442 5446 5447 5450 5451 5453 X . X ROWER 74LS00 74LS02 74LS03 74LS04 74LS05 74LS08 74LS09 74'^SIO 74LS11 •74LS12 74LS13

Contextual Info: M O TO R O LA <8> SN54/74LS09 m r r r r r r r Lsÿ Ls[> "¿ P 7] Q U A D 2-INPUT A N D GATE [~~r^ LOW POWER SCHOTTKY □ n i in l i t e t tir □ ‘ O PEN COLLECTOR OUTPUTS J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 {Plastic) GUARANTEED OPERATING RANGES

lm294oct

Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Contextual Info: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12

IC TTL 7432

Abstract: 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn

ls 7409

Abstract: 74LS09PC m1375 7409DC 5409DM 54S09DM 7409PC 74LS09DC 74S09DC 74S09PC
Contextual Info: 09 C O N N E C T IO N DIA G R A M P IN O U T A • Vt54/7409 ^ 4 S /7 4 S 0 9 ^ A V/54LS/74LS09 & o 6 QUAD 2-INPUT AND GATE W ith O p e n -C o lle cto r Output O R D E R IN G CO D E: See S e ctio n 9 PIN PKGS OUT C O M M E R C IA L GRADE M ILITA R Y GRADE

Contextual Info: g MOTOROLA SN54/74LS09 QUAD 2-INPUT AND GATE QUAD 2-INPUT AND GATE Vcc LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 LU LU LU L±J LU LsJ Ld GND *OPEN COLLECTOR OUTPUTS N SUFFIX „r ç p ïï cmeS m D SUFFIX SOIC CASE 751A-02 5 ORDERING INFORMATION SN54LSXXJ

751A-02

Contextual Info: M M O TO R O LA SN54/74LS09 QUAD 2-INPUT AND GATE Q U A D 2-IN P U T A N D GATE Vcc rm îïïi rjâi h nói it i LOW POWER SCHOTTKY m I_5dJ rr3 ) J SUFFIX CERAMIC CASE 632-06 GND •OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 D SUFFIX SOIC CASE 751A-02

Contextual Info: I LS TTL DN74LS Series 74LS09 74LS09 Quad 2-input Positive AND Gates with Open Collector Outputs • Description DN 74LS09 contains four 2-input positive isolation AND gate circuits w ith open collector outputs. P-1 ■ Features • • • • “W ired” AND capability