LS49 Search Results

4LS48

Abstract: 74LS47 functions decoder 7448 input 4 LS 74LS47 decoder 74LS47 54L47
Contextual Info: TYPES SN5446A, ’47A, ’48, ’49, SN54L46, ’L47, SN54LS47, ’LS48, ’LS49, SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS M A R C H 1974. R E V IS E D D E C E M B E R 1983 '48, 'LS48 feature '49, 'LS49 feature

Contextual Info: Ä M O T O R O L A D ESCRIPTIO N — The S N 54LS/74 LS490 contains a pair of high­ speed 4-stage ripple counters. Each half of the SN 5 4LS/7 4 LS490 has individual Clock. Master Reset and Master Set (Preset 9} inputs. Each section counts in the 8 ,4 , 2 , t BCD code.

Contextual Info: LS498A National Semiconductor LS498A/LS498A Octal Shift Register General Description The LS498A is an 8-bit synchronous shift register with paral­ lel load and hold capability. Two function-select inputs lo, l-i provide one of four operations which occur synchronous­

DM74LS491N

Contextual Info: LS491 S National Semiconductor LS491/LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

Contextual Info: LS49 National Jüt Semiconductor LS49 BCD to 7-Segment Decoder General Description The LS49 translates four lines of BCD 8421 Input data into the 7-segment numeral code as shown in the Function Table. It has open-collector outputs and is logically the 14pin verson of the ’48, without the lamp test and ripple blank­

MC74LS247

Abstract: MC74LS147 MC74LS08 MC74LS373 MC74LS00 MC74LS245 LS30 ls30 diode MC74LS38 MC74LS32
Contextual Info: HC Portfolio Comparison PART # LS00 LS01 LS02 LS03 LS04 LS05 LS06 LS07 LS08 LS09 LS10 LS11 LS12 LS13 LS14 LS15 LS20 LS21 LS22 LS26 LS27 LS28 LS30 LS31 LS32 LS33 LS37 LS38 LS40 LS42 LS47 LS48 LS49 LS51 LS54 LS55 LS73 LS74 LS75 LS76 LS77 LS78 LS83 LS85 LS86

DM54LS498J

Abstract: DM74LS498J DM74LS498N J24F N24C LS498
Contextual Info: LS498 a National Semiconductor LS498/LS498 Octal Shift Register General Description The LS498 is an 8 -bit synchronous shift register with parallel load and hold capability. Two function select inputs lo, l-t provide one of four operations which occur synchronously

C1995

Abstract: DM54LS498 DM54LS498J DM74LS498 DM74LS498J DM74LS498N J24F N24C
Contextual Info: LS498 LS498 Octal Shift Register General Description The LS498 is an 8-bit synchronous shift register with parallel load and hold capability Two function select inputs I0 I1 provide one of four operations which occur synchronously on the rising edge of the clock (CK)

74ls491

Abstract: 200II
Contextual Info: LS491 531 National JuM Semiconductor LS491/LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB's, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

74ls48 PIN OUT

Contextual Info: <8> M OTOROLA D E S C R IP T IO N — The S N 54LS /74LS 48 and S N 54LS /74LS 49 are BCD to 7-Segm ent Decoders consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. The LS49 offers active HIGH opencollector outputs for current-sourcing applications to drive logic circuits

Contextual Info: July 1989 Semiconductor LS498/LS498 Octal Shift Register General Description The LS498 is an 8-bit synchronous shift registe r w ith parallel load and hold capability. T w o fun ctio n se le ct inputs lo, h provide one o f fo u r opera tio ns w hich o ccu r synchronously

Contextual Info: LS498 5 2 National Semiconductor LS498/LS498 Octal Shift Register General Description The LS498 Is an 8 -bit synchronous shift register with parallel load and hold capability. Two function select inputs lo, h provide one of four operations which occur synchronously

N7448B

Abstract: LS 74LS47 BCD seven segment SN7448 ttl ic 7448 sn7446
Contextual Info: SN5446A, '47A, ’48, SN54LS47, 'LS48, 'LS49, SN7446A, '47A, '48, SN74LS47, ’ LS48, ‘LS49 BCD TO SEVEN-SEGMENT DECODERS/DRIVERS M AR C H 1 9 7 4 -R E V IS E D M AR C H 1 9 8 8 '48, LS48 feature '46A, '47A, LS47 feature LS49 feature Open-Collector Outputs

SN741S47

Abstract: sn74l47 7SK22 SN7464 74L32 L848 BCD-to-seven-Segment Decoders SN74L46
Contextual Info: TYPES SN5446A, '47A, '48. 49. SN54L46, L47, SN54LS47, LS48, LS49. SN7446A, '47A, '48, SN74L46. L47. SN74LS47, LS48, LS49 BCO-TO-SEVEN-SEGMENT DECODERS/DRIVERS B U L L E T IN N O . P L -S 7 6 1 1 8 1 1 . M A R C H 1 9 7 4 - R E V I S 6 D O C T O B E R 1 9 7 6

Contextual Info: LS491A a National Semiconductor LS491A/LS491A 10-Bit Counter General Description Features The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

KKZ 09

Abstract: kkz 12 LS496 VS213 VS-209 kkz 10
Contextual Info: S G S-THOMSON 81C 07E D I 7^=1537 ÜOiaaOfl & I t o 19379 n — _ - ~ ~ T-52-13-35 -, r 7 I ’¿r LS496 QUAD RELAY DRIVER The inputs with small All inputs and voltage The LS496 is a monolithic integrated circuit for driving four mechanical bipolar relays. In ad­

54LS490DMQB

Abstract: 54LS490FMQB DM54LS490M DM54LS490N J16A LS490 M16A
Contextual Info: I NATIONAL SEflICON» -CLOfilO 31E D • bS01122 0Q7D17T t ■ LS490 National Semiconductor LS490/LS490 Dual Decade Counter General Description Features The ’LS490 contains a pair of high speed 4-stage ripple counters. Each half of the 'LS490 has individual Clock, Mas­

74LS49

Contextual Info: S N 5 4 4 6 A , '4 7 A , '4 8 . S N 5 4 L S 4 7 , 'L S 4 8 , SN7446A, 4 7 A , '4 8 . S N 7 4 L S 4 7 . 'L S 4 8 , LS49, LS49 BCD TO SE VEN-SEG M ENT DECODERS/DRIVERS M A R C H 1 9 7 4 —REVISED M A R C H 1 9 8 8 '48. 'LS48 feature '46A, '47A, 'LS47 feature

PB-14

Contextual Info: LS490 National Semiconductor LS490/LS490 Dual Decade Counter General Description Features The 'LS490 contains a pair of high speed 4-stage ripple counters. Each half of the 'LS490 has individual Clock, Mas­ ter Reset and Master Set Preset 9 inputs. Each section

Contextual Info: LS498 Egl National J jI Semiconductor LS498/LS498 Octal Shift Register General Description The LS498 is an 8-bit synchronous shift register with parallel load and hold capability. Two function select inputs lo, h provide one of four operations which occur synchronously

54LS

Abstract: 54LS49 54LS49DMQB 54LS49FMQB J14A LS249 W14B BI312
Contextual Info: LS49 National Semiconductor LS49 BCD to 7-Segment Decoder General Description The LS49 translates four lines of BCD 8421 Input data into the 7-segment numeral code as shown In the Function Table. It has open-collector outputs and Is logically the 14pin verson of the '48, without the lamp test and ripple blank­

54LS490

Abstract: 54LS490DMQB 54LS490FMQB DM54LS490M DM54LS490N J16A LS490 M16A N16E
Contextual Info: LS490 National Semiconductor LS490/LS490 Dual Decade Counter General Description Features The ’ LS490 contains a pair of high speed 4-stage ripple counters. Each half of the 'LS490 has individual Clock, Mas­ ter Reset and Master Set Preset 9 inputs. Each section

n 10221

Abstract: 10221 DM54LS498A DM54LS498AJ DM74LS498A DM74LS498AJ DM74LS498AN DM74LS498AV J24F N24C
Contextual Info: LS498A LS498A Octal Shift Register General Description The LS498A is an 8-bit synchronous shift register with parallel load and hold capability Two function-select inputs I0 I1 provide one of four operations which occur synchronously on the rising edge of the clock (CK)

free of ic 74LS90

Abstract: 74LS90 IC 74LS90 FEATURES pin diagram of ic 74ls90
Contextual Info: February 1992 Semiconductor LS490 Dual Decade Counter General Description Features The ’LS490 contains a pair of high speed 4-stage ripple counters. Each half of the 'LS490 has individual Clock, Mas­ ter Reset and Master Set Preset 9 inputs. Each section