74LS368A Search Results

74LS368AP

Contextual Info: MITSUBISHI LSTTLs M 74LS368AP H E X BUS D R IV E R W IT H 3 -S T A T E O U TPU T IN V E R T E D DESCRIPTION The M 7 4L S 36 8A P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing 6 buffers w ith 3-state outputs and is provided

Contextual Info: I LS TTL DN74LS Series 74LS368A 74LS368A Hex Bus Drivers with 3-state Outputs • Description P-2 DN 74LS368A contains six 3-state o u tp u t inverter buffer circuits w ith outp u t-control inputs G! and G2 for four and two circuits respectively. ■ Features

Contextual Info: GD54/74LS368A HEX TRI-STATE INVERTING BUFFERS Description This device contains six independent gates each of which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capabili­

74LS367A

Abstract: LS365A 74LS366A
Contextual Info: SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A M MOTOROLA 3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D) paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power

M74LS368AP

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 74LS368AP HEX BUS DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 7 4L S 36 8A P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing 6 buffers w ith 3-state outputs and is provided w ith ou tp ut control

DN74LS368A

Abstract: MA161
Contextual Info: I 74LS368A LS T T L DN74LS Series 74LS368A Hex Bus D rivers with 3 -s ta te Outputs • Description P-2 DN 74LS368A contains six 3-state o u tp u t inverter buffer circuits w ith o u tp u t-control inputs G j and G2 for four and two circuits respectively.

Contextual Info: 368A y CO NNECTION DIAGRAM PINOUT A / 54LS/74LS368A HEX 3 -IN P U T IN VERTER BUFFER W ith S e p a ra te 2 -B it a n d 4 -B it S e ctio n s ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) OUT A CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%,

truth table NOT gate 74

Abstract: LS365A truth table 74LS365A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls367a LS366
Contextual Info: SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A 3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit / 4-bit, with inverting or non-inverting data D paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power

74LS368APC

Abstract: 74LS368AP 54LS368ADM 54LS368AFM 74LS368ADC 74LS368AFC icc 312
Contextual Info: 368A y y C O N N E C T IO N D IAG RAM P IN O U T A 54LS/74LS368A HEX 3-IN PU T INVERTER BUFFER With S eparate 2-B it and 4-B it Sections O R D E R IN G C O D E: See S e c tio n 9 P IN PKGS P la stic D IP (P) OUT A C O M M E R C IA L GRADE M IL IT A R Y G RADE

Contextual Info: 8 < > SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A MOTOROLA 3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data D paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power

74LS365A

Abstract: 74LS366A LS365A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS367A E16-D
Contextual Info: SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A 3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit / 4-bit, with inverting or non-inverting data D paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power

LS365A

Contextual Info: SN54LS/74LS365A SN54LS/74LS366A SN54LS/74LS367A SN54LS/74LS368A MOTOROLA D ES C R IP T IO N — These devices are high speed hex buffers w ith 3 -sta te outputs. They are organized as single 6 -b it or 2 -b it/4 -b it, w ith inverting or non-inverting data D paths. The outputs are designed to

Contextual Info: SN54LS/74LS365A SN54LS/74LS366A SN54LS/74LS367A SN54LS/74LS368A MOTOROLA D ESCR IPTIO N — T he se devices are high speed hex buffers with 3-state outputs. They are organized a s single 6-bit or 2-bit/4-bit, with inverting or non-inverting data D paths. The outputs are designed to

STK411-230E

Abstract: STK411-220E stk442-130 PAL005A UPC2581V FN1016 STRG6153 RSN313H25 STK407-070B MCZ3001D
Contextual Info: R Serving The Electronic Industry Since 1982 Ordering at Dalbani is so easy Go to : www.dalbani.com Search & check stock Busque y revise nuestro inventario A Search Enter your Item number and click GO Entre el numero del producto y haga clicsobre GO The system will take you straight to the Item that you are looking for

BPW22A

Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
Contextual Info: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

JM38510/01405BEA

Abstract: SN74368A SN54LS367A-SP M38510 SN74367A SN54365A
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-9687802QEA OBSOLETE CDIP

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

SNJ54LS

Abstract: SN74LS367AN JM38510/01405BEA SN74368A LS365A 74LS365A LS367A SN54LS367A-SP M38510 SN74367A
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-9687802QEA OBSOLETE CDIP

74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Contextual Info: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC

lvc16244

Abstract: BC240 2sk3174 CBT1G125 LV2GT14A HC32 Hitachi HA13557A transistor 2SC1162 H8 hitachi programming manual 30204SP
Contextual Info: HITACHI ELECTRONIC COMPONENTS DATABOOK 2003 INDEX General Informations Multi Perpose Products Safety Considerations Hitachi Semiconductor Package Databook HITACHI Sales Locations Diodes Microcontroller Microcontroller General Microcontroller Overview List

74LS36

Abstract: 74LS367A
Contextual Info: <g> SN54/74LS365A SN54/74LS366A SN54/74LS367A MOTOROLA D E S C R I P T I O N — T h e s e d e v ic e s a re h ig h s p e e d h e x b u ffe rs w ith 3 -s ta te o u tp u ts . T h e y a re o rg a n iz e d a s s in g le 6 -b it o r 2 - b it / 4 - b it , w it h

SNJ54366AJ

Abstract: JM38510/01405BEA SN74368A SN54LS367A-SP M38510 SN74367A SN54365A
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9687802QEA OBSOLETE CDIP