74LS36 Search Results

DN74LS366A

Abstract: MA161
Contextual Info: 74LS366A LS TTL DN74LS Series 74LS366A 74 LSSfeCPr Hex B u s D riv e r s with 3 - s t a * e Outputs • Description D N 74LS366A P -2 c o n t a in s s ix 3 -state o u tp u t^ in v e rte r b u ffe r c ir c u it s w ith c o m m o n o u tp u t - c o n t r o l in p u ts G i a n d G 2 .

Contextual Info: GD54/74LS367A HEX BUS DRIVERS WITH 3-STATE OUTPUTS Feature • 3-State Outputs Drive Bus Line or Buffer Memory Address Registers • Choice of True or Inverting Outputs Pin Configuration Vcc G2 6A 6Y 5A 5Y 4A 4Y Description These hex buffers and line drivers are designed

1N3064

Abstract: 1N916 74LS 74LS363 N74LS363N
Contextual Info: Signelics 74LS363 L a tc h Octal Transparent Latch With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit transparent latch • 3-state MOS compatible output buffers • Common Latch Enable input with hysteresis • Common 3-state Output Enable

74LS364

Abstract: 1N3064 1N916 74LS N74LS364N
Contextual Info: Signetics 74LS364 Flip-Flop Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT TOTAL 50MHz 42mA • 8-bit positive edge-triggered register • 3-State MOS compatible output buffers

74LS364

Abstract: 1N3064 1N916 74LS N74LS364N
Contextual Info: 74LS364 Signetics Flip-Flop Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit positive edge-triggered register • 3-State MOS compatible output buffers • Common Clock input with hysteresis • Common 3-State Output Enable

74LS366AP

Contextual Info: MITSUBISHI LSTTLs M 74LS366AP H EX BUS D R IV E R W IT H 3 -S T A T E O UTPUT IN V E R T E D DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74LS366AP is a semiconductor integrated circu it containing 6 buffers w ith 3-state outputs and is provided w ith

74LS368AP

Contextual Info: MITSUBISHI LSTTLs M 74LS368AP H E X BUS D R IV E R W IT H 3 -S T A T E O U TPU T IN V E R T E D DESCRIPTION The M 7 4L S 36 8A P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing 6 buffers w ith 3-state outputs and is provided

Contextual Info: 367A CO NNECTIO N DIAGRAM PINOUT A J / 54LS/74LS367A HEX 3 -S T A T E BUFFER '• A W ith S e p a ra te 2 - B it a n d 4 - B it S e c tio n s ^ ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) OUT A CO M M ERCIAL GRADE M ILITARY GRADE = V cc +5.0 V ±5%,

Contextual Info: 74LS366A LS TTL DN74LS Series 74LS366A Hex Bus D rivers with 3-sta*e Outputs • Description P-2 D N 74LS366A contains six 3-state output_ inverter buffer circuits w ith com m on output-control inputs G i and G2 . ■ Features • • • Com m on o u tp u t-control inputs for all six circuits

Contextual Info: I LS TTL DN74LS Series 74LS368A 74LS368A Hex Bus Drivers with 3-state Outputs • Description P-2 DN 74LS368A contains six 3-state o u tp u t inverter buffer circuits w ith outp u t-control inputs G! and G2 for four and two circuits respectively. ■ Features

Contextual Info: 74LS364 Signetics Flip-Flop Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit positive edge-triggered register • 3-State MOS compatible output buffers TYPE 74LS364 TYPICAL SUPPLY CURRENT TOTAL f M AX 50MHz 42mA

Contextual Info: GD54/74LS368A HEX TRI-STATE INVERTING BUFFERS Description This device contains six independent gates each of which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capabili­

rca 236

Abstract: 74ls365 74466 81ls96 74LS366 74796
Contextual Info: — 23 6 — Octal 3-State Bus Buffers 7 4 4 6 6 8 1 LS96 81LS96 74L S365, 74LS366«8b itK S xn E H ( i t ) T IW L S465, L S 4 6 6 U P N P A * o 7 4796 t |bJ I; IN rtif] H OUT tpd max tp d max h -L 1 tp d max !^ H A tp d max Z -» L tp d max tp d max Icc

CI 7408

Abstract: CI 74LS08 TTL 74ls21 74LS21 7407 connection diagram 54LS CI 7413 7432 TTL fairchild 74LS125 7408 and
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L - T T L D65 54/7413, 54LS/74LS13 Vcc NC R R R fü| FÖI f71 r«l D66 54/74125, 54LS/74LS125 D67 54/74126, 54LS/74LS126 Vcc Vcc äJ QND E D68 54LS/74LS365 j y E D O 3X 5 rn m D O E D D O E D O IPTJ? ~ ? f i r

1N3064

Abstract: 1N916 74LS 74LS363 N74LS363N equivalent fa 5515
Contextual Info: 74LS363 Latch S ignetics Octal Transparent Latch With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit transparent latch • 3-state MOS compatible output buffers • Common Latch Enable input with hysteresis • Common 3-state Output Enable

HI-21

Abstract: pn74ls364 7t6d
Contextual Info: PANASONIC 69328f2 IN D L/ELE K PANASONIC -CICÏ 7E » Ë J bTBEflSE IN O L * E L E C T R O N IC 0[][]7a30 □ 7 2 C 0 7 2 30 LS TTL DN74LSS/U-X . 74LS364/74LS364S “ ö ~ 7 - C b5~ DN 74LS364/ 74LS364S Octal Positive Edge-Triggerd D-Type Flip-Flops with 3 - s ta te Outputs

74LS367A

Abstract: LS365A 74LS366A
Contextual Info: SN54/74LS365A SN54/74LS366A SN54/74LS367A SN54/74LS368A M MOTOROLA 3-STATE HEX BUFFERS These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D) paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power

Contextual Info: I LS TTL DN74LS Series 74LS365A 74LS365A Hex Bus Drivers with 3 -state Outputs P-2 • Description D N 74LS365A contains six 3-state o u tp u t buffer circuits w ith com m on outp u t-co n trol inputs G! and G2 . ■ Features • • High fan-out ( I o l = 24m A , I o h = —2.6m A )

74LS268

Abstract: 74468 L1327 74LS367 81LS98 A4016 IC-JJ
Contextual Info: — 238 — 7 4 4 6 8 8 1 LS98 VCC 5 2 8A Octal 3-State Bus BY 7 A 7Y 6A 6Y 5A 5Y IqJ IjjJ H> 'fh 1*1 fh fh LiinininiMtinininiMJ G1 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND 81 L S 98 O 74LS367, 74LS268«8bit«fe o 74798 ¿ M b ms K-h IN OUT H ALSK F S AS AC ACT HC HCU

74LS364

Contextual Info: 74LS364 Signetics Flip-Flop Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit positive edge-triggered register • 3-State MOS compatible output buffers • Common Clock input with hysteresis • Common 3-State Output Enable

74LS364

Contextual Info: 74LS364 Signelics Flip-Flop Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit positive edge-triggered register • 3-State MOS compatible output buffers • Common Clock input with hysteresis • Common 3-State Output Enable

8bit latch 74ls

Abstract: 74LS363 5v vcc buffer latch
Contextual Info: 74LS363 Signetics Latch Octal Transparent Latch With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit transparent latch • 3-state MOS compatible output buffers • Common Latch Enable input with hysteresis • Common 3-state Output Enable

GD74

Contextual Info: GD54/74LS365A HEX-BUS DRIVERS; 3-STATE OUTPUTS, NON-INVERTED DATA OUTPUTS Feature Pin Configuration • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Choice of True or Inverting Outputs G2 . G2 A L L Y L L L H L H X X Z X H X Z 5Y

M74LS368AP

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 74LS368AP HEX BUS DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 7 4L S 36 8A P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing 6 buffers w ith 3-state outputs and is provided w ith ou tp ut control