GD74 Search Results

GD74F244

Contextual Info: @ LG Semicon. Co. LTD. Pin Configuration Description The GD74F244 is octal buffer and line driver designed to be employed as memory and address drivers, clock drivers and busoriented transmitter/receivers which pro­ vide improved PC and board density. 1G

Contextual Info: GD74F245 PRELIMINARY DATA SHEET OCTAL BIDIRECTIONAL TRANCEIVER WITH TRI-STATE INPUTS/OUTPUTS Features • Non-Inverting Buffers • Bidirectional Data Path • B Outputs Sink 64 mA Description The ‘F245’ contains eight non-inverting bi­ directional buffers with TRI-STATE outputs

gd74f125

Contextual Info: @ LG Semicon. Co. LTD. Description The GD74F125 contains 4 buffers with 3-State outputs and is_provided with an output control input C which is indep­ endent for each buffer. Function Table (each buffer) Inputs C A L L L H H X Fin Configuration Vcc 4C 4A

Contextual Info: GD74F373 PRELIMINARY DATA SHEET OCTAL D-TYPE FLIP-FLOP WITH TRI-STATE OUTPUTS Features • 8 latches in a single package Pin Configuration • 3-State Bus driving outputs Description The GD74F373 contains eight latches with TRI-STATE outputs for bus-organized system

GD74F08

Contextual Info: GD74F08 PRELIMINARY DATA SHEET QUAD 2-INPUT AND GATE Description Pin Configuration This device contains four independent 2input AND gates, each of which performs the Boolean functions Y = A»B or Y = Â+B. Function Table each gate Inputs A Outputs B Y H

GD74F125

Contextual Info: GD74F125 PRELIMINARY DATA SHEET QUAD BUFFER TRI-STATE Description The G D 74F 12 5 contains 4 buffers with 3-State outputs and is provided with an output control input (C) which is indepen­ dent for each buffer. Pin Configuration VCC 4A T Function Table (each gate)

Contextual Info: GD74F04 PRELIMINARY DATA SHEET HEX INVERTER Description Pin Configuration The GD74F04 contains 6 logic inverters which accept standard TTL input signal and standard TTL output level. They have a greater noise margin than conventional inverters. Vcc 6Y 6A 5Y

Contextual Info: GD74F374 PRELIMINARY DATA SHEET OCTAL D-TYPE FLIP-FLOP WITH TRI-STATE OUTPUTS Features • 8 D-type flip-flops in a single package • Buffered positive edge-triggered clock • 3-State Bus Driving outputs Pin Configuration Description The GD74F374 is a high speed, low-power,

Contextual Info: GD74F32 PRELIMINARY DATA SHEET QUAD 2-INPUT AND GATE Description Pin Configuration This device contains four independent 2input OR gates, each of w hjch performs the Boolean functions Y = A»B or Y = A+B. Function Table each gate Inputs A Outputs B Y H L

4 bit even parity generator circuit

Contextual Info: » 111 1— — T'lS 2 -3 / 0*^1723 GD74't7fl 1 I T E X A S I N S T R -CLÔGIC3- SN74ALS29833, SN74ALS29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D2990, FEBRUARY 1987-REVISED JULY 1987 Functionally Similar to AMD AM29833 and AM29834 SN74ALS' . . . DW OR NT PACKAGE

Contextual Info: @ LG Semicon. Co. LTD. Pin Configuration Description The GD74F257 is a quad 2-input multiplexer with 3-State outputs. Four bits of data from two sources can be selected using a Common Data Selected input. The four outputs present the selected data in true non-inverted form.

Contextual Info: @ LG Semicon. Co. LTD. Description The GD74F373 contains of eight latches with 3 -State outputs for bus organized system application. The flip-flops appear transparent to the data when Latch Enable G is High. When G is Low, the data that meets the setup

GD74F08

Contextual Info: PRELIMINARY DATA SHEET GD74F08 QUAD 2-INPUT AND GATE Description This device contains four independent 2input AND gates, each of which performs the Boolean functions Y = A»B or Y = A+B. Function Table each gate Inputs Outputs A B Y H H H L X L X L L X Im m a te r ia l

GD74F244

Contextual Info: GD74F244 PRELIMINARY DATA SHEET OCTAL BUFFER/LINE DRIVER WITH NON-INVERTED TRI-STATE Features • 3-State outputs drive bus line or buffer memory address registers • Output sink 64 mA • 15 mA source current • Input clamp diodes limit high speed termination effects

GD74F374

Contextual Info: @ LG Semicon. Co., LTD. Description The GD74F374 is a high-speed, low-power octal D-type flip-flop featuring separate Dtype inputs for each flip-flop and 3-State outputs for bus-oriented applications. A buf fered Clock CK and Output Control (DC) are common to all flip-flops.

Contextual Info: GD74F74 PRELIMINARY DATA SHEET DUAL D- TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP Description Pin Configuration The GD74F74 is dual D-type positive edge trig­ VCC CLR2 02 CK2 PR2 Q2 Q2 [T4~| R 3I fTil FmH Rpl |T | f i l gered flip-flop with Direct Clear CLR and Set

Contextual Info: GD74F151 PRELIMINARY DATA SHEET 8-INPUT MULTIPLEXER Features Pin Configuration • Select one-of-eight data lines. • Performs parallel-to-serial conversion. • Permits multiplexing from N line to one line. • Also for use as Boolean function generation.

GD74LS373

Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feautre • • • • • 8 Latches in a Single Package 3-State Bus-Driving Outputs Full Paralle-Access for Loading Buffered Control Inputs Clock/Enable input Has Hysteresis to Improve

Contextual Info: GD74F00 PRELIMINARY DATA SHEET QUAD 2-INPUT NAND GATE Description Pin Configuration This device contains four independent 2-input NAND gates, each o f which perform s the Boolean Pin F unction Vcc functions Y=A*B or Y= A+B. 4B 4A 4Y Function Table each gate

Contextual Info: GD74F257 PRELIMINARY DATA SHEET QUAD 2-INPUT MULTIPLEXER WITH TRI-STATE OUTPUTS Features • 3-State outputs interface directly with system bus • Non-inverting 3-State outputs Description The GD74F257 is a quad 2-input multi­ plexer with TRI-STATE outputs. Four bits

GD74F04

Contextual Info: GD74F04 PRELIMINARY DATA SHEET HEX INVERTER Description The GD74F04 contains 6 logic inverters which accept standard TTL input signal and standard TTL output level. They have a greater noise margin than conventional inverters. Pin Configuration Vcc 6Y 6A 5Y

LS640-1

Contextual Info: GD54/74LS640, GD74LS640-1 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUT INVERTED Features Pin Configuration • • Inverting 3-STATE buffer outputs Bi-directional Bus Transceivers in High-Density 20-Pin Packages • Hysteresis at Bus Inputs Improves Noise Margins

GD74F74

Contextual Info: LG Semicon. Co. LTD. Description Pin Configuration The GD74F74 is a dual D-type positive edge triggered flip-flop with Direct Clear CLR and Set inputs (PR) and complementary outputs(Q,Q). Clock triggering occurs at a voltage level of the clock pluse and is not

GD74LS373

Abstract: GD74LS
Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feature • • • • • 8 Latches in a Single Package 3-State Bus-Driving Outputs Full Paralle-Access for Loading Buffered Control Inputs Clock/Enable input Has Hysteresis to Improve