74179 IC Search Results

Contextual Info: 179 CONNECTION DIAGRAM PINOUT A a 54/74179 4-B IT SHIFT REGISTER m r D E SC R IPTIO N — The ’179 features synchronous parallel or serial entry, asynchronous reset and parallel outputs, with the complement output of the fourth stage also available. The flip-flops are fully edge-triggered, with state

74179

Abstract: 74178 ttl 74178 ScansUX986
Contextual Info: TTL/MSI 93178/54178, 74178 93179/54179, 74179 4-BIT SHIFT REGISTERS -! B F AN N O U N CED D E S C R IP T IO N — The 9 3 1 7 8 and 9 3 1 7 9 are 4 -B it S h ift Registers w ith b o th serial and pa rallel data e n try c a p a b ility . The 9 3 1 7 9 features a d ire c t reset

K155LE1

Abstract: K155LA8 K155AG3 K155LA3 K155LP5 K155AG1 K155TM2 K155KP2 k155tl2 K155TL1
Contextual Info: Table of Equivalent TTL-IC Values [This table is reprinted from the December 1985 RadioAmater, the journal of the Yugoslavia Amateur Radio Society.— Ed.] NATIONAL SEMICOND NEC RFT USSR FAIRCHILD SIEMENS PHILIPS DM8000N ftPB201 D110C K155LA3 FJH131 FLH101

SN74179

Abstract: SN54178 SN74178 1972-REVISED
Contextual Info: TYPES SN54178, SN54179, SN74178, SN74179 4-BIT PARALLEL-ACCESS SHIFT REGISTERS DECEM BER * Typical M axim um Clock Frequency . . . 39 M H z SN54178 . . . J OR W PACKAGE f • 1 9 7 2 -R E V IS E D D E C E M B E R 1 9 8 3 SN74178 . . . J OR N PACKAGE Three Operating Modes:

74179 register ic

Abstract: 74179 4 bit shift register
Contextual Info: TYPES SN54178, SN54179, SN74178, SN74179 4-BIT PARALLEL-ACCESS SHIFT REGISTERS D E C E M B E R 1 9 7 2 -R E V IS E D O EC EM B • • Typical Maximum Clock Frequency . . . 39 MHz ■ • V 1 | Three Operating Modes: Synchronous Parallel Load Right Shift Hold Do Nothing}

IC TTL 7432

Abstract: IC 7402, 7404, 7408, 7432, 7400 ttl 74118 74189 memory ic 74138 74189 ttl memory TTL 74289 RC4458 IC 74373 ttl 74592
Contextual Info: Test and Measurement Systems Electronic Manufacturing Services ABI Electronics Limited Dodworth Business Park Barnsley S75 3SP South Yorkshire United Kingdom Tel: +44 0 1226 207420 Fax: +44 (0)1226 207620 www.abielectronics.co.uk ChipMaster Compact Professional IC List

74179 register ic

Abstract: IC 74178 74179 4 bit shift register
Contextual Info: TYPES SN54178, SN54179, SN74178, SN74179 4-BIT PARALLEL-ACCESS SHIFT REGISTERS D E C E M B E R 1 9 7 2 -R E V IS E D D E C E M B E R 1983 Typical Maximum Clock Frequency . . . 39 MHz • Three Operating Modes: S N 7 4 1 7 8 . . . J OR N P A C K A G E TO P V IE W

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

74179 4 bit shift register

Abstract: 74179 ic SN74179 74179 register ic 74179
Contextual Info: TTL MSI TYPES SN54178. SN54179, SN74I78. SN74T7S 4-BIT PARALiiL ACCESS SHIFT REGISTERS _ B U L L E T I N NO . O L-S 721 18 46 . D E C E M B E R 1972 Typical Maximum Clock Frequency . . . 39 MHz S N 6 41 78 . . . J O R W P A C K A G E

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

74LS167

Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
Contextual Info: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.

IC 7402, 7404, 7408, 7432, 7400

Abstract: 7408, 7404, 7486, 7432 CI 74122 ci 7445 CI 7442a ci 74174 7402, 7404, 7408, 7432, 7400 LM 7408 lm 7486 IC 7444
Contextual Info: 54/74 ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) LOW LEVEL PARAMETER V|H (V ) HIGH LEVEL OUTPUT VOLTAGE V|C (V) CLAMP VOLTAGE VOL (V) LOW LEVEL INPUT CURRENT VO H(V) HIGH LEVEL l,L (mA) LOW LEVEL VCC=MIN V|N=* TEST CONDITIONS Vc c ^ M IN

truth table for ic 74138

Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Contextual Info: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture

16 bit comparator using 74*85 IC

Abstract: 74LSI39 74LS80 shift register 74ls96 4 bit synchronous ic 7476 74ls150 74LS94 74ls91 counter OAI211 74ls179
Contextual Info: EKG-3-8805 CMOS Gate Array 5GF Series • O u tlin e T he R icoh gate a rray 5GF series com plies w ith th e CMOS 1.5 m rule, and o ffe rs high speed o p e ra tio n w ith a gate delay tim e o f 1.0 ns. T he 5G F series in h e rits th e rich lib ra ry o f th e 5GH series, and th e S R A M and mask RO M can be used

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder
Contextual Info: s I SEMICONDUCTOR GROUP 23E D • t?54E40 G00fl535 1 "T-q2-q \ p a rtII CMOS STANDARD CELL LSI MSM91H000 SERIES ¿U S' This M a terial C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r O K I SEMICONDUCTOR GROUP 23E D ■ b72M240 DGGÔ23b G

16CUDSLR

Abstract: 7474 D flip flop free alu 74382 counter schematic diagram 74161 sn 74373 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151 IC 74373 truth table
Contextual Info: PLDS-MAX & PLS-MAX M MAX+PLUS Program mable Logic Developm ent System & Software M Data Sheet September 1991, ver. 1 □ □ □ □ □ □ □ □ □ S o ftw a re su p p o rt for M A X 5000 M u ltip le A rray M atriX E PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 74154 shift register IC sk 7443 full adder circuit using ic 74153 multiplexer DN 74352 full adder using ic 74138 74183 adder pin function of ic 74390 7478 J-K Flip-Flop
Contextual Info: FUJITSU MICROELECTRONICS FUJITSU 37417bH 0010SÔ3 23E D MB65XXXX MB66XXXX MB67XXXX AV CMOS SERÍES GATE ARRAYS ~ June 1986 Edition 2.0 : T - 4 2 - n - o °i DESCRIPTION S The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

7408, 7404, 7486, 7432 use NAND gate

Abstract: JLCC-68 ci 74386 cI 74150 jLCC68 74153 full adder 7402, 7404, 7408, 7432, 7400 74106 sln 7404 LCC-64
Contextual Info: MB65XXXX MB66XXXX MB67XXXX AV CMOS SERIES GATE ARRAYS F U JIT S U June 1986 Edition 2.0 DESCRIPTION The Fujitsu MB65xxxx/M B66xxxx/M B67xxxx family are a series o f high perform ance CMOS gate arrays designed to provide high density, low pow er, and operating speeds th a t are com parable to standard bipolar logic. The A V M 865xxxx series is an ideal

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 full adder using Multiplexer IC 74151 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 DN 74352 circuit diagram for IC 7483 full adder application of ic 74153 ic 74148 block diagram 74191, 74192, 74193 circuit diagram
Contextual Info: MB65XXXX MB66XXXX MB67XXXX AV CMOS SERIES GATE ARRAYS F U JIT S U June 1986 Edition 1.0 DESCRIPTION The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high density, low power, and operating speeds that are comparable to standard bipolar logic. The AV MB65xxxx series is an ideal

74LS382

Abstract: C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381
Contextual Info: ix u jD U Lu ra n ctiu F U JIT S U _ mmm CWiOS Gate Array GENERAL INFORMATION The Fujitsu CMOS gate array family consists of twentyeight devlcs types which are fabricated with advanced silicon gate CMOS technology. And more than 14devlc«s are coming. Fujitsu CMOS gate array are configured In a

counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74151 8 by 1 Multiplexer flip flop 74379 74175 flip flops
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

ALU IC 74381

Abstract: encoder IC 74147 16CUDSLR 74139 truth table alu 74382 truth table for 7446 from ic 7447 truth table IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
Contextual Info: PLDS-HPS, PLS-HPS, PLS-OS & PLS-ES A N & * r a \ MAX+PLUS II Programmable Logic Development System & Software Data Sheet S eptem ber 1991, ver. 1 U M A X + P L U S II is the single, u nified d e velo p m e n t system for A lte ra 's C lassic, M A X 5000, M A X 7000, and S T G E P L D s .