truth table for ic 74138
Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Contextual Info: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture
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44-mbyte386-basedtruth table for ic 7413816cudslr+8alu ic 74183ic 74151 diagram and truth table74183 alu74147 pin diagram and truth tablepin diagram of ic 74184hp-7475a7408 ic truth tableic 74373 truth table
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D5032
Abstract: IC TTL 7400 free J1810 Altera LP5 PLDS-ENCORE plej5128
Contextual Info: PLDS-ENCORE MAX+PLUS, A+PLUS & SAM+PLUS Programmable Logic Development System Data Sheet September 1991, ver. 2 Contents □ □ □ □ □ General Description P L S -M A X — M A X + P L U S P ro g ra m m ab le Logic Softw are P L S - S U P R E M E — A + P L U S P ro g ra m m a b le L ogic Softw are
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j1810j5064pled910486-based+5d5032ic ttl 7400 freealtera lp5plds-encoreplej5128
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EPLD 5128
Contextual Info: September 1991, ver. 2 Introduction Application Brief 73 Altera provides a variety of softw are utility pro gra m s that co m p le m e n t the M A X + P L U S II, M A X + P L U S , A + P L U S , S A M + P L U S , a n d M C M a p d ev elop m en t systems. These pro gram s are available via Altera's electronic bulletin board service
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800-epld11-compatibleepld 5128 |
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schematic diagram cga to vga
Abstract: TTL 7400 TTL 7400 full
Contextual Info: PLS2 V A A+PLUS PROGRAMMABLE LOGIC USER SOFTWARE DI Q O I L Ù L FEATURES GENERAL DESCRIPTION • Software support for all Altera General-Purpose EP-Series EPLDs. A+PLUS, Altera Programmable logic user software, contained in the PLS2 product, is a series of software
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schematic diagram cga to vgattl 7400ttl 7400 full |
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TTL 74139
Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at
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ttl 7413974153 muxmsi 7414816cudslr+6ci 74138sn 743738mcomp7404 7408 74327408, 7404, 7486, 7432flip-flop 7471
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shiftregisters
Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock
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shiftregistersep910altera ttl library74ls series logic gates+674lsep1810ep1810-45ep610ple40altera logicaps ttl library
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Altera EP1800
Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.
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ep1800altera ep1800ep1800 jedec formataltera logicaps ttl library+3schema pa built upep1800 logic diagramep18001
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53413
Abstract: 58725 632367 594971
Contextual Info: Altera Digital Library CD-ROM December 2002 CD-ADL2002-4.0 Legal Notice This CD ROM contains documentation and other information related to products and services of Altera Corporation “Altera” which is provided as a courtesy to Altera’s customers and potential customers. By copying or using any information contained on this CD ROM, you agree to be bound by the
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cd-adl2002-4incorpora6596re37060re35977+45341358725632367594971
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ALTERA EP1810LC-45
Abstract: EP1810LC-45 EP1810LC-35 EP1810JC-45 EP1810jC-35 EP1810JC EP1810LC45
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBRUARY 1989-R E V IS E D AUGUST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic CHIP-CARRIER PACKAGE
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ep181048-macrocelld32321989-r+833-mhzaltera ep1810lc-45ep1810lc-45ep1810lc-35ep1810jc-45ep1810jc-35ep1810jcep1810lc45
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full adder using ic 74138
Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Contextual Info: EP1800JC-EV1 EP1800JC-EV1 EVALUATION CHIP • Advanced CHMOS circuitry features low power, high performance, and high noise immunity power consumption, high noise margins, and ease of design. The EP1800 is implemented in a sub 2-micron dual-polysilicon CHMOS floating gate EPROM tech
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ep1800jc-ev1ept80068-pin0ut20+130ut21out220ut23full adder using ic 74138full adder using multiplexer ic 74151decoder ic 74138ttl 7419474151 multiplexerpin configuration of ic 74138application of multiplexer ic 74151ic 7413874138 ic decodermultiplexer ic 74151
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9852
Abstract: schematic diagram vga schematic diagram cga to vga
Contextual Info: PLE40 \ LOGIC APS SCHEMATIC CAPTURE SOFTWARE PLE40 CONTENTS GENERAL DESCRIPTION SOFTWARE Digital logic designs are often o rigin ally con ceived in the form of a logic or schematic diagram. The engineer wishing to take advantage of the many benefits of the new high density program
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9852schematic diagram vgaschematic diagram cga to vga |
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74194 shift register
Abstract: 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191
Contextual Info: €Pßl400 PROGRAMMABLE BUS PERIPHERAL FEATURES GENERAL DESCRIPTION • Bus I/O —Register Intensive Buster EPLD The EPB1400 (Buster) EPLD from Altera repre sents the firs t M icro proce ssor Peripheral UserConfigurable at the Silicon level. The device consists
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25mhzepb140074194 shift register74377 register+8logicapsshift register by using d flip-flop 747474191 counter74377latches 74373altera logicaps ttl library74374 74373ttl 74191
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IC 74373
Abstract: IC 74373 truth table logitech 99 mouse IC function of latch ic 74373
Contextual Info: USER-CONFIGURABLE r Q Q 1 /1 0 0 MICROPROCESSOR PERIPHERAL E r D I ^ H J U \ GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive B U S T ER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions. Byte-Wide Microprocessor Bus Port with
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32-bit25mhzdri22epb1400+4ic 74373ic 74373 truth tablelogitech 99 mouse icfunction of latch ic 74373
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EPS448
Abstract: Altera EP1800 altera ep320
Contextual Info: Surface-Mount EPLDs 20 to 28-Lead Package Supplement Data Sheet March 1990 This supplement provides the specifications for Altera's 20-, 24-, and 28-pin plastic surface-mount packaging options. The specifications consist of physical dimensions and thermal characteristics for plastic Small Outline
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28-lead28-pinep330ep630+8epm5016epm5024epm5032300-m20-pineps448altera ep1800altera ep320
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Altera LP5
Abstract: Altera EP1800 logicaps schematic capture EPM5016 EP1810 PLEj1810 PLDS-MAX ep330 EPS448D 02D-00209
Contextual Info: AN Ü □ !^ V a \ Product Selection Guide Data Sheet September 1991, ver. 2 In t r o d u c t io n P r°d u c t Selection G uid e summarizes the range of products available from Altera: U □ U Ü U U U General-purpose E P L D s Function-specific E P L D s
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pleg5192pled448plej448plej464+16plmj464pleq464plej2001p600/610/610a/610t/630p900/910/910a/910t800/1810/1810t/1830altera lp5altera ep1800logicaps schematic captureepm5016ep1810plej1810plds-maxep330eps448d02d-00209
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EP1200
Abstract: Altera ep1200
Contextual Info: ry T \ u s e r -c o n fig u r a b le MICROPROCESSOR PERIPHERAL C D D U n n C i D I t U U GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive BUSTER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions.
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32-bit25mhzepb1400ep1200+1altera ep1200
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PL-ASAP
Abstract: altera EP300 Altera EP1800 EP1200 ple3-12a altera LP4 Altera ep1200 ep320 EPS448 EPMS130
Contextual Info: Datasheet EPB2001 and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM PS/2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
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epb2001c0m90c84pl-asapaltera ep300+8altera ep1800ep1200ple3-12aaltera lp4altera ep1200ep320eps448epms130
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EPB2001LC
Abstract: altera ep320 altera EP300 EP600 programming program altera ep320 COM90C84 PLDS-MCMAP EPM5127 altera LP4 PLEJ2001
Contextual Info: EPB2001 D atasheet and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM P S /2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
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epb2001epb2001lcaltera ep320altera ep300+7ep600 programmingprogram altera ep320com90c84plds-mcmapepm5127altera lp4plej2001
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EP1810JC-35
Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBHUARY 1989-REVISED AUGUST 1989 CHIP-CARRIER PACKAGE Erasable, U ser-Configurable LSI Circuit C apable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic
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ep181048-macrocelld32321989-revised+1333-mhz68-pin28cllep1810jc-35programming manual ep910ep1810lc-35olc-45ep1810jc35programming manual epldep1810li-45ep1810jcep1810ierasable programmable logic device
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7400 databook
Abstract: 7400 TTL logitech TTL LS 7400
Contextual Info: TTL schematic designs processed and imple mented in EPLDs by Altera. Two programmed EPLDs returned to you. PLSTART coupon good for processing two designs. Runs on IBM XT, AT and compatible personal computers. Graphical entry of logic schematics: — Design schematics using TTL MacroFunctions
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7400 databook7400 ttllogitechttl ls 7400 |
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74245 BUFFER IC
Abstract: pin diagram of 74245 BUFFER IC IC 74245 latch 74373 80386 microprocessor pin out diagram 74245 buffer 74373 cmos dual s-r latch 74245 BIDIRECTIONAL BUFFER data 74245 20 pin ic Ob2 tube
Contextual Info: V 7 \ USER-CONFIGURABLE m ic r o p r o c e s s o r p e r ip h e r a l C D D 1/100 L rD I4 U U FEATURES GENERAL DESCRIPTION • Bus I/O — Register Intensive BUSTER EPLD. • Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral
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32-bit25mhzepb1400-2epb1400+11100pf74245 buffer icpin diagram of 74245 buffer icic 74245latch 7437380386 microprocessor pin out diagram74245 buffer74373 cmos dual s-r latch74245 bidirectional buffer data74245 20 pin icob2 tube
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EP1810JC-45
Abstract: logicaps schematic capture manual programming manual EP910 Flip flop JK cmos
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLO D3232, FEB RU ARY 1 9 8 9 -R E V IS E D AU GU ST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic
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ep181048-macrocelld323233-mhz+4ep1810jc-45logicaps schematic capture manualprogramming manual ep910flip flop jk cmos
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PLS-SAM
Abstract: logicaps schematic capture PLED448 PLS-MAX PLEJ5128
Contextual Info: g _ n V A \ 1 1— /— vA PR O G RA M M ABLE LOGIC DEVELOPM ENT SYSTEM -ENCO RE n i H O r ilH A n f P L D S ^ N IÜ H E PLDS-ENCORE CONTENTS GENERAL DESCRIPTION • • • • • • • PLDS-ENCORE is the most comprehensive EPLD development software package available. It sup
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pled5032plej5128pled448pled1400+412-monthpls-samlogicaps schematic capturepls-max
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