EPM5064 Search Results

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

Contextual Info: EPM5064 EPLD Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpu as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over

EPM5128LC

Abstract: epm5128jc MPM5128LC
Contextual Info: MPLDs Mask-Programmed Logic Devices Data Sheet September 1991, ver. 1 □ □ □ Features □ □ □ □ □ □ General Description Masked versions of EPLD designs Reduced cost for large-volume applications Available for EP1810, EPM5032, EPM5064, EPM5128, EPM5130,

EPM5064

Abstract: EPM5064-1
Contextual Info: EPM5064 EPLD Features □ □ □ □ □ □ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 63 MHz 128 shareable expander product terms "expanders" allowing over

EPM5130

Abstract: J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
Contextual Info: MAX 5000 M M M & Programmable Logic Device Family , J a n u a r y 1 9 9 8 . v e r. 4 F e a tu re s . D a ta S h e e t m • ■ ■ Table 1. MAX5000 Device Features EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3,750 Macrocells

EPM5064

Contextual Info: MPM5064 MPLD Features □ □ □ IJ □ □ J □ General Description C M O S , M a s k - P r o g r a m m e d L o g ic D e v i c e M P L D c a p a b l e of im p l e m e n tin g h ig h - d e n s ity c u s to m logic functio ns H ig h - v o lu m e r e p la c e m e n t for EPM5064 EPLD d e s ig n s

Contextual Info: EPM5064 EPLD Features □ □ □ □ □ General Description High-density 64-macrocell general-purpose MAX 5000 EPLD 128 shareable exp ander p rodu ct term s providing flexible logic expansion Over 32 product terms in a single macrocell 64 additional latches provided by cross-coupled expanders

Contextual Info: MPM5064 MPLD Features □ □ □ □ □ □ □ □ General Description CMOS, M ask-Program m ed Logic Device MPLD capable of implementing high-density custom logic functions High-volume replacement for EPM5064 EPLD designs Zero-power operation (typically 15 (iA standby)

Contextual Info: EPM5064 EPLD Features □ □ □ □ □ General Description High-density 64-macrocell general-purpose MAX 5000 EPLD 128 shareable expander product terms providing flexible logic expansion Over 32 product terms in a single macrocell 64 additional latches provided by cross-coupled expanders

EP320DM

Abstract: EP600DM883B EPM5128GM883B EP320DM883B EP1800GM883B EP1800GM ep310dm883b EP600DM EP910dm EP1810GM883B
Contextual Info: Military Products / A 1 b Data Sheet September 1991, ver. 2 In trO d U C tiO n T ab les 1 throu gh 7 p ro v id e inform ation on m ilitary-tem p eratu re-ran g e, M I L - S T D - 8 8 3 B - q u a l i f i e d , a n d D E S C i l’ L D s. F o r d e t a ile d i n f o r m a t i o n , re fe r

program EPM5032

Abstract: ACCEL Technologies epm5032 Valid Logic Systems
Contextual Info: 1 /Â \l u /A ^ September 1991, ver. 3 In tro d u c tio n *-1 “ V Ï\ Third-Party Development & Programming Support Data Sheet Altera re cognizes the im portance of third-party s u p p o rt tools and w orks closely with m any third-party vend ors to ensure high-quality s upp ort for

J-Lead, QFP ceramic

Abstract: IC 7400 SERIES book EPM 5192
Contextual Info: M A X 5000 Programmable Logic Device Family March 1995, ver. 2 Features. D a ta she et • ■ ■ ■ ■ ■ ■ Advanced M ultiple Array M atrix MAX 5000 architecture com bining speed and ease-of-use of PAL devices w ith density of program m able gate arrays

7483 adder/subtractor

Abstract: ic 7483 full adder ttl 7483 FULL ADDER of IC 7483 7483 full adder 7483 adder
Contextual Info: Understanding MAX 5000 & Classic Timing January 1998, ver. 2 Introduction A pplication Note 78 Altera devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays

XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative

EPM9560RC304-15

Abstract: EPM7064SLC44-10 vhdl code for ARQ EASY 21653 EPC1 price epc1213 EPM5064 EPM7032S through hole chip carriers Lexra PLMQ7192/256-160NC
Contextual Info: Newsletter for Altera Customers ◆ Fourth Quarter ◆ November 1998 Quartus: Altera’s Fourth-Generation Development Tool With Altera’s new QuartusTM software, programmable logic development tools enter the multi-million-gate era. This powerful fourthgeneration software meets

EPF6016TC144-3

Abstract: relay Re 04501 re 04501 relay USART 8251 lms algorithm using vhdl code C8251 NEC RELAY 10PIN 5V 8251 uart vhdl PDN9516 verilog code for Modified Booth algorithm
Contextual Info: Newsletter for Altera Customers ◆ Second Quarter ◆ May 1998 Altera Unveils FLEX 10KE Devices Altera recently unveiled enhanced versions of FLEX ␣ 10K embedded programmable logic devices— FLEX 10KE devices. Fabricated on a 0.25-µm, five-layer-metal process with a 2.5-V core, FLEX 10KE

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

1962a

Abstract: lt1196 LTC1196 LTC1196-1AC LTC1196-1BC LTC1196-2AC LTC1198 LTC1198-1AC LTC1198-1BC LTC1198-2AC
Contextual Info: LTC1196/LTC1198 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options U DESCRIPTIO FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Sampling Rates: 1MHz LTC1196 750kHz (LTC1198) Low Cost SO-8 Plastic Package Single Supply 3V and 5V Specifications

PLMG7192-160

Abstract: 6000FLEX PLMT7000-44 PLMJ1213 ep910 ieee PLMG5130A PLMT1064 PLMG5192A PLMJ7000-84 PLMG5128A
Contextual Info: 開発ツール セレクタ・ガイド January 1999 アルテラのプログラマブル・ロジック開発ツールの概要 アルテラは業界でもっとも高速でもっともパワフルな、そしてもっ とも柔軟性の高いプログラマブル・ロジック開発用ソフトウェアとプ

Device-List

Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Contextual Info: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which

EPM5130

Abstract: EPM5064 MC3334 44 pin plcc socket program EPM5032 EPMS128 EPM5064-1
Contextual Info: MAX 5000 Programmable Logic Device Family Jan ua ry 1998. ver. 4 F e a tu r e s . Data S heet • ■ ■ ■ ■ ■ ■ ■ Advanced M ultiple A rray MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices w ith the density of

LT1198

Abstract: EMP5064 LTC1407A-1 LTC1196 LTC1196-1AC LTC1196-1BC LTC1196-2AC LTC1198 LTC1198-1AC LTC1198-1BC
Contextual Info: LTC1196/LTC1198 8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options FEATURES n n n n n n n n n n n n DESCRIPTION High Sampling Rates: 1MHz LTC1196 750kHz (LTC1198) Low Cost Single Supply 3V and 5V Specifications Low Power: 10mW at 3V Supply 50mW at 5V Supply

EPM5128GM

Abstract: EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 epm5130qc EPM5130QC-2 EPM5032DC-20 EPM5032DC-15 EPM5130LC
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5130

Abstract: EPM5016
Contextual Info: E P M 5016 to E P M 5192 E PLD s High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.