EPLD 5128
Abstract: EPM5128-1 K942
Contextual Info: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over
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7400series
Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns
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EPLD 5128
Abstract: EPM5120-2
Contextual Info: EPM5128 EPLD Features □ □ H ig h -d en sity 128-m acrocell g en era l-p u rp o se M A X 5000 EPLD 256 sh areab le ex p a n d e r p ro d u ct term s th at allow ov er 32 p ro d u ct term s in a sin gle m acro cell H ig h -sp eed m u lti-L A B a rch itectu re
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EPM5192
Abstract: PLMJ5192 154-10 plcc 68 EPM5128 PLEJ5128 Altera EPM5128 PLMG5192A PLEG5128
Contextual Info: PCN NUMBER 9407 MAX 5000 PRODUCT CHANGE NOTIFICATION Overview The MAX 5000 product line will be transitioned from a 0.8 micron EPROM process to a 0.65 micron EPROM process. This change will improve Altera’s ability to support the product line on a long term basis. This notification addresses the EPM5128 and
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51h11
Abstract: C1058
Contextual Info: EPM 5128 E PLD Features • ■ ■ ■ ■ ■ Figure 14. EPM5128 Package Pin-Out Diagrams Package outlines not drawn to scale. See Tables 4 and 5 in this data sheet fo r pin-out information. Windows in ceramic packages only. , nnnnnnnnnnnnnnnnn i/o c I/O c
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EPM5128LC
Abstract: epm5128jc MPM5128LC
Contextual Info: MPLDs Mask-Programmed Logic Devices Data Sheet September 1991, ver. 1 □ □ □ Features □ □ □ □ □ □ General Description Masked versions of EPLD designs Reduced cost for large-volume applications Available for EP1810, EPM5032, EPM5064, EPM5128, EPM5130,
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Altera EPM5128
Abstract: K941 EPM5128 K1188 L883 Altera 48-macrocell application 74series
Contextual Info: EPM 5128 EPLD Figure 14. EPM5128 Package Pin-Out Diagrams Package outlines no t drawn to scale. See Tables 4 and 5 in this data sheet fo r pin-out information. Windows in ceramic packages only. . nn n nnn n nnnnnnnnnn I/O C I/O c 3 I'O 3 i/o I/o c I/o c □ I/O
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EPM5130
Abstract: J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
Contextual Info: MAX 5000 M M M & Programmable Logic Device Family , J a n u a r y 1 9 9 8 . v e r. 4 F e a tu re s . D a ta S h e e t m • ■ ■ Table 1. MAX5000 Device Features EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3,750 Macrocells
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multiplexor 74151
Abstract: 74151 PIN DIAGRAM counter schematic diagram 74161 Altera EPM5128 EPM5128 74151 74151 multiplexer 7400 databook jk 7400 counter schematic diagram 74151
Contextual Info: / A Nu a nvA \ 128 M ACROCELL HIGH d e n s it y FEATURES CONNECTION DIAGRAM h hH K i-ii-ini-innni-ii-innnni-innn - CO LO TT CO CM 8 I'D <8 <8 3 2 1 <0 EPM5128 c'icowciCOcoeoirococoTr^ 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 Vcc 53 I/O 52 I/O 51 I/O 50 GND
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74series
Abstract: Altera EPM5128
Contextual Info: ALTERA CORP bflE D m 05^5372 DG03321 MIM H A L T EPM 5128A EPLD Features □ High-density, second-generation MAX 5000 EPLD developed on an advanced 0.65-micron CMOS EPROM process Higher-speed upgrade for existing EPM5128 designs High-speed multi-LAB architecture
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5128A
Abstract: EPLD 5128
Contextual Info: EPM 5128A EPLD Features □ □ Preliminary Information □ □ □ High-density, second-generation MAX 5000 EPLD developed on an advanced 0.65-m icron CM OS EPROM process Higher-speed upgrade for existing EPM5128 designs High-speed multi-LA B architecture
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Altera EPM5128
Abstract: EPM5128 EPM5128-1 K941 DSTS372 EPM5128-2 EPM5128A-15 EPM5128A-20 K1188
Contextual Info: EPM5128 EPLD Figure 14. EPM5128 Package Pin-Out Diagrams Package outlines no t drawn to scale. See Tables 4 and 5 in this data sheet fo r pin-out information. Windows in ceramic packages only. . n n n n nn n n n n n nnn nn n I/O C I/O c 3 I'O □ I/O □ i/o
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EP320DM
Abstract: EP600DM883B EPM5128GM883B EP320DM883B EP1800GM883B EP1800GM ep310dm883b EP600DM EP910dm EP1810GM883B
Contextual Info: Military Products / A 1 b Data Sheet September 1991, ver. 2 In trO d U C tiO n T ab les 1 throu gh 7 p ro v id e inform ation on m ilitary-tem p eratu re-ran g e, M I L - S T D - 8 8 3 B - q u a l i f i e d , a n d D E S C i l’ L D s. F o r d e t a ile d i n f o r m a t i o n , re fe r
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J-Lead, QFP ceramic
Abstract: IC 7400 SERIES book EPM 5192
Contextual Info: M A X 5000 Programmable Logic Device Family March 1995, ver. 2 Features. D a ta she et • ■ ■ ■ ■ ■ ■ Advanced M ultiple Array M atrix MAX 5000 architecture com bining speed and ease-of-use of PAL devices w ith density of program m able gate arrays
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XC3030-70PC84C
Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative
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ccd board driver
Abstract: TC217 dc iris driver direct drive auto-iris iris driver control drive coil RS170 SR30-10R-6S amphenol 3110
Contextual Info: MULTICAM MC-1134P Multimode Very-High-Resolution B/W Camera User’s Guide JULY 1993 SOCU002C B-1 Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
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7486 XOR gate
Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier
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PLMG7192-160
Abstract: 6000FLEX PLMT7000-44 PLMJ1213 ep910 ieee PLMG5130A PLMT1064 PLMG5192A PLMJ7000-84 PLMG5128A
Contextual Info: 開発ツール セレクタ・ガイド January 1999 アルテラのプログラマブル・ロジック開発ツールの概要 アルテラは業界でもっとも高速でもっともパワフルな、そしてもっ とも柔軟性の高いプログラマブル・ロジック開発用ソフトウェアとプ
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Device-List
Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Contextual Info: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which
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EPM5130
Abstract: EPM5064 MC3334 44 pin plcc socket program EPM5032 EPMS128 EPM5064-1
Contextual Info: MAX 5000 Programmable Logic Device Family Jan ua ry 1998. ver. 4 F e a tu r e s . Data S heet • ■ ■ ■ ■ ■ ■ ■ Advanced M ultiple A rray MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices w ith the density of
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CD2400
Abstract: EPM5128 EPM5192 Z89165 Z89166
Contextual Info: Z89C6500ZDB CPS DC-5002-01 CUSTOMERPROCUREMENTSPECIFICATION Z89C6500ZDB Z8 DSPTADCONTROLLER DAUGHTERBOARD DESCRIPTION KIT CONTENTS The Z89C6500ZDB is a daughter board that provides emulation support for Zilog’s Z89C65, Z89C66, Z89165 and Z89166 microcontrollers. This includes all the essential MCU timing and I/O circuitry which simplifies user
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PCN9510
Abstract: plcc 68 epm5128a
Contextual Info: PRODUCT CHANGE NOTIFICATION Overview The Classic product family is being transitioned to a 0.65-micron process. This change will improve Altera’s ability to support the product line on a long-term basis. The new die revisions will be pin, function, timing and programming-file compatible with existing die
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EPM5128GM
Abstract: EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 epm5130qc EPM5130QC-2 EPM5032DC-20 EPM5032DC-15 EPM5130LC
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays
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EPM5130
Abstract: EPM5016
Contextual Info: E P M 5016 to E P M 5192 E PLD s High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
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