TPEC Search Results

Contextual Info: C1NETECH INDUSTRIAL CO.,LTD. Product tpecitc*lon Power chip resistors size 1218 MECHANICAL DATA 5%; 1% O u tlin e s M a*a par 100 u n its TYPE MASS 0 RMC-28 3 M arking AM resistors w itiin the E24 series are marked with a 3-digit code and a 4digit code for resistors of the E96

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

TCO-2112

Abstract: AD9516
Contextual Info: 14-Output Clock Generator AD9516-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

25CC

Abstract: AM2952 MB2052 MB2052B
Contextual Info: T -5 2 ~ 3 -£ S Philips Semiconductors Advanced BiCMOS Products Objective specification Dual octal registered transceiver 3-State PHILIPS INTERNATIONAL FEATURES • StE D • 7110fl2fc. □03clclll 7S3 H P H I N QUICK REFERENCE DATA CONDITIONS T«ni> = 25CC; GND = 0V

Contextual Info: 54AC11175, 74AC11175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR T 10109— D3388, DECEMBER 1989— REVISED MARCH 1990 • Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators 5 4 A C 11 1 75 . . . J P A C K A G E 74A C 11175 . . . DW O R N PACKAGE

NE6753

Abstract: audiom PHILIP A7 A7B0 D053 NE5753 NE5753D NE5753DK SA5752 SA5753
Contextual Info: PHILIPS INTERNATIONAL bOE » • ?110fi2b 0053^03 T3T « P H I N Objective pacification Philip« Sem iconductor* RF Communication* Product* NE/SA5753 Audio processor-filter and control section DESCRIPTION FEATURES The NE/SA5753 is a high performance low power CMOS audio signal processing system

Contextual Info: APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

W39L020

Contextual Info: W39L020 256K x 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W39L020 is a 2Mbit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. For flexible erase capability, the 2Mbits of data are divided into 4 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The byte-wide × 8 data appears on DQ7 − DQ0.

77V011

Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Contextual Info: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.

MT8952

Abstract: MT8976 MT8977 MT8977AC MT8977AE MT8977AP MT8979 MT8980 SLC96
Contextual Info:  ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

MH89790

Abstract: MH89790B MH89790BN MH89790BS
Contextual Info: ST-BUS FAMILY MH89790B CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information  Features • • • • • • • • • • • • • • • ISSUE 5 Complete primary rate 2048 kbit/s CEPT transceiver with CRC-4 option Selectable HDB3 or AMI line code

Contextual Info: D S 1 31 4 PRELIMINARY DS1314 3V Nonvolatile Controller with Lithium Battery Monitor DALLAS SEMICONDUCTOR FEATURE PIN ASSIGNMENT • Converts CMOS SRAM into nonvolatile memory • Unconditionally write-protects SRAM when Vcc is out of tolerance ^ ^cci VccoOC

Contextual Info: DS2223/DS2224 DALLAS DS2223/DS2224 EconoRAM s e m ic o n d u c to r FEATURES PACKAGE OUTLINE • Low-cost, general-purpose, 256-bit memory - DS2223 has 2 56-bit SRAM - DS2224 has 32 -bit ROM, 224-bit SRAM T O -9 2 • Reduces control, address and data interface to a

651102

Abstract: av can 100 1p0 ir1f PEPI sc-fr LC6500 LC651104N tv service mode IQ TFT 9.2" k999A cr-e5
Contextual Info: number : EN 4958 Ordering CMOS LSI LC 651104N /F /L , II N o .4958 SA%YO 651102N /F /L Single-Chip 4-Bit Microcomputer For Small-Scale Control-Oriented Applications I / / / ,'V V-' ./ / :íí.*• "x N

Contextual Info: EL2260C/EL2460C Dual/Quad 130 MHz Current Feedback Amplifiers H GH PERFORMANCE ANALOG INTEGRATED CIRCUITS Features General Description • 130 M H z 3 dB b andw idth Av = + 2 • 180 M H z 3 dB bandw idth (A v = + 1 ) • 0.01% differential gain, R l = 500ft

Contextual Info: DS1585/DS1S07 PRELIMINARY DALLAS DS1585/DS1587 Serialized Real Time Clocks SEMICONDUCTOR PIN ASSIGNMENT FEATURES Incorporates industry standard DS1287 PC clock plus enhanced features: x iC X2C • 64-bit Silicon serial number • Power control circuitry supports system power on

ACS8510

Abstract: ACS8520 ACS8522 ACS8530 ACS8946 GR-253
Contextual Info: ACS8946 JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE ADVANCED COMMUNICATIONS Introduction FINAL Features The ACS8946 JAM PLL is a Jitter-Attenuating, Multiplying differential Phase-Locked Loop, for generating low jitter

ACS9510

Abstract: icp multiplexer 24 pin ACS8510 ACS8520 ACS8522 ACS8525 ACS8530 ACS8947T QFN48
Contextual Info: ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path COMMUNICATIONS ADVANCED COMMS & SENSING Introduction FINAL Features The ACS8947T JAM PLL is a general pupose, Integer N, jitter-attenuating, differential phase-locked loop for

command cathode 7 SEGMENT DISPLAY LT 543

Abstract: 82801IBM intel chipset 845 motherboard repair pml 003 am intel chipset 845 motherboard repair circuit 7 SEGMENT DISPLAY COMMON CATHODE lt 543 82801ibm ich9m PC MOTHERBOARD intel 845 circuit diagram mobile MOTHERBOARD CIRCUIT diagram ICH9
Contextual Info: Intel I/O Controller Hub 9 ICH9 Family Datasheet – For the Intel® 82801IB ICH9, 82801IR ICH9R, 82801IH ICH9DH, 82801IO ICH9DO, 82801IBM ICH9M and 82801IEM ICH9M-E, and ICH9M-SFF ICH9-I/O Controller Hubs August 2008 Document Number: 316972-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

mbus

Abstract: SK 8022 ace dsc hen nu SM 8002 C
Contextual Info: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.

nRF24L01 pa lna

Contextual Info: nRF24L01 Single Chip 2.4GHz Transceiver Product Specification Key Features • • • • • • • • • • • • • • • • • • Worldwide 2.4GHz ISM band operation Up to 2Mbps on air data rate Ultra low power operation 11.3mA TX at 0dBm output power

Contextual Info: nRF24LE1 OTP Ultra-low Power Wireless System On-Chip Solution Product Specification v1.2 Key Features • • • • • • • • • • • nRF24L01+ 2.4 GHz transceiver 250 kbps, 1 Mbps and 2 Mbps air data rates Fast microcontroller (8051 compatible)

nRF24L01

Abstract: nRF24L01 pa lna RF NRF24L01 nRF24l01 mouse double pipe data sheet marking code DN SMD nRF2401 4x4 keyboard nRF24L01-EVKIT Transceiver nRF24L01
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION nRF24L01 Single chip 2.4 GHz Transceiver FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • • • True single chip GFSK transceiver Complete OSI Link Layer in hardware

Tco 2112 245.76 MHz

Abstract: TCO-2112 ADF4106 AD9511 Rev a
Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM VS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers