77V400 Search Results

4413

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 osam marking code
Contextual Info: SECTION 2 77V400 Switching Memory 2.1 77V400 Switching Memory Description The 77V400 Switching Memory is designed to provide essential data path functionality for switches, concentrators and expanders in Asynchronous Transfer Mode ATM Networks. The 77V400 supports aggregate data throughput at rates up to 1.24 Gbps and has 8192

77V011

Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Contextual Info: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.

mbus

Abstract: SK 8022 ace dsc hen nu SM 8002 C
Contextual Info: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.

256K DPRAM

Abstract: IDT70914 IDT709149 70V261 70V25 70V24
Contextual Info: SYNCHRONOUS DUAL-PORT STATIC RAMS FOR DSP AND COMMUNICATION APPLICATIONS APPLICATION NOTE AN-144 Integrated Device Technology, Inc. By Jeffrey C. Smith ABSTRACT The Sequential Access Random Access Memory The first of the synchronous components to be presented

3606

Contextual Info: PRELIMINARY 77V400 SWITCHStAR ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports • Byte Addition or Byte Subtraction for x4/x8 to x l 6/x32

IDT77155

Abstract: IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 3606
Contextual Info: SWITCHStARTM ATM CELL BASED 8 X 8 PRELIMINARY 1.24Gbps NON-BLOCKING 77V400 INTEGRATED SWITCHING MEMORY Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip supports an 8 x 8 port switch at 155Mbps per port Fusion MemoryTM technology utilized to provide the

IDT77V1264L200

Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

DSLAM

Abstract: 77V011 77V012 77V1054 77V1253 77V1254 77V400 77V500 77V550 DSLAM HEADER
Contextual Info: DSLAM Digital Subcriber Line Access Multiplexer Application Brief #5 Introduction The Digital Subscriber Line Access Multiplexer DSLAM is a communications device that transmits and receives digital signals from multiple Digital Subscriber Lines (xDSL) over copper subscriber loops.

Contextual Info: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.

77V011

Abstract: 77V400 IDT77011 IDT77V011 IDT77V400 IDTV400 intel 8008 cpu
Contextual Info: IDT77V011 Data Path Interface DPI to Utopia Level 2 Translation Device )HDWXU WXUHV ‹ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). ‹ Ideal for xDSL DSLAM and 25Mbps switching applications. ‹ Supports ATM Forum UTOPIA Level 2 interface in both 8-bit

ATM25

Abstract: IDT77V1264L200 ST6200T
Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

Contextual Info: Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA - 95054 Phone #: 408 727-6116 Fax #: (408) 727-2328 PRODUCT DISCONTINUANCE NOTICE (PDN) PDN #: Last Buy Date: I01-01 Issue Date: 06/14/01 06/14/02 Last Ship Date: 09/14/02 (3 months after last buy date)

adsl splitter dslam circuit diagram

Abstract: D link adsl modem board flow switch water pump circuit diagram for 3 phase DSLAM structure HDSL Modem circuit diagram DSLAM board fiber dsl
Contextual Info: Integrated Device Technology ADSL ADSL System System Solutions Solutions Broadband Access Technology Integrated Device Technology Copyright 1997, Integrated Device Technology, Inc 1 1 1 Integrated Device Technology Possible Possible Services Services Over

RX 433

Contextual Info: IDT77V1254L25 Quad Port PHY Physical Layer for 25.6 and 51.2 ATM Networks Features List ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels

L9939

Abstract: B897 k9920 L9924 k1917 JESD22-B100 K9928 K2837 P9848 h9910
Contextual Info: INTEGRATED DEVICE TECHNOLOGY, INC. QUALITY & RELIABILITY MONITORS October 1999 2975 Stender Way, Santa Clara, CA 95054 TEL: 800 345-7015 FAX: (408) 492-8674 QUALITY & RELIABILITY MONITOR REPORT October 1999 TABLE OF CONTENTS Section I: Introduction Section II:

77V400

Abstract: 77V500 IDT77010 IDT77155 IDT77V400 IDT77V500 OC-24
Contextual Info: WAN Concentrator Design using SWITCHStARTM Introduction APPLICATION BRIEF AB-223 SWITCHStAR Advantages The Wide Area Network WAN is a high-performance, ATM based network that facilitates long distance communication. A key function in this network is the need to concentrate lower speed ATM traffic and feed it into

Contextual Info: ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP ADVANCED INFORMATION 77V400 SWITCHING MEMORY Integrated D e v ie TechnoJogy, lie . FEATURES: • Byte Addition or Byte Subtraction fo r x8 to x16/x32 U topia conversion capability • Internal header C yclical R edundancy C he ck CRC and

B1416

Abstract: E1113 1CS MARKING IDT77V400 IDT77V500 IDT77V550 13-bitcell m1416 s156 A1516
Contextual Info: 77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory Features List ! Single chip supports an 8 x 8 port switch at 155Mbps per port ! Central Memory Architecture eliminates Head-of-Line Blocking by sharing the memory array with all ports

DT77V500

Contextual Info: ADVANCED INFORMATION IDT77V550 SWITCHStAR SWITCH MANAGER D escrip tio n F eatures * * * * Interprets switch command cells from external work The IDT77V550 Switch Manager is a device developed to provide a station and loads the command into the IDT77V500 Switch

Contextual Info: 1.2 Gbps 8 port ATM Switch IDT SwitchBIOS Programmer’s Guide Revision 4.0.1 Date 4/28/1999 Table of Contents Chapter 1 INTRODUCTION. 4 1.1 Data Path Overview. 4

77V400

Abstract: 77V500 IDT77500 IDT77V011 IDT77V012 IDT77V400 IDT77V500 V400 OD031
Contextual Info: Page 1 of 35 Application Note 258 SwitchStar Cell-Bus Operation with 2.5Gbps ATM Switch Example SwitchStar Cell-Bus The SwitchStar Cell-Bus mode enables multiple SwitchStar chipsets to be combined in a scalable architecture to provide greater bandwidth than a single chipset. Individually,

nrzi clock recovery

Abstract: 77V1254 IDT77V1254 P3TC SF1153
Contextual Info: Quad Port PHY Physical Layer for 25.6 and 51.2 Mbps ATM Networks PRELIMINARY IDT77V1254 Integrated Device Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels

sm 8013

Abstract: 77V011 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Contextual Info: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.

ATM25

Abstract: IDT77V1264L200 ST6200T
Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ! ! ! ! ! ! ! ! ! ! ! ! ! Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for